49 lines
1.7 KiB
Python
49 lines
1.7 KiB
Python
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from migen.flow.actor import *
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from migen.actorlib import structuring, dma_asmi, spi
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from milkymist.dvisampler.common import frame_layout
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class DMA(Module):
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def __init__(self, asmiport):
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self.frame = Sink(frame_layout)
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self.shoot = CSR()
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###
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sof = Signal()
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parity_r = Signal()
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self.comb += sof.eq(self.frame.stb & (parity_r ^ self.frame.payload.parity))
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self.sync += If(self.frame.stb & self.frame.ack, parity_r.eq(self.frame.payload.parity))
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pending = Signal()
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frame_en = Signal()
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self.sync += [
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If(sof,
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frame_en.eq(0),
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If(pending, frame_en.eq(1)),
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pending.eq(0)
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),
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If(self.shoot.re, pending.eq(1))
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]
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pack_factor = asmiport.hub.dw//32
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self.submodules.packer = structuring.Pack(list(reversed([("pad", 2), ("r", 10), ("g", 10), ("b", 10)])), pack_factor)
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self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw, reverse_from=False)
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self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_EXTERNAL)
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self.comb += [
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self.dma.generator.trigger.eq(self.shoot.re),
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self.packer.sink.stb.eq(self.frame.stb & frame_en),
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self.frame.ack.eq(self.packer.sink.ack | (~frame_en & ~(pending & sof))),
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self.packer.sink.payload.r.eq(self.frame.payload.r << 2),
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self.packer.sink.payload.g.eq(self.frame.payload.g << 2),
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self.packer.sink.payload.b.eq(self.frame.payload.b << 2),
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self.packer.source.connect(self.cast.sink, match_by_position=True),
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self.cast.source.connect(self.dma.data, match_by_position=True)
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]
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def get_csrs(self):
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return [self.shoot] + self.dma.get_csrs()
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