dvisampler: mostly working, very basic and slightly buggy DMA
This commit is contained in:
Sebastien Bourdeauducq
parent
f82a16f3a3
commit
e2d15b169a
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@ -1,8 +1,6 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.actorlib import structuring, dma_asmi, spi
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from migen.bank.description import AutoCSR
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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@ -10,11 +8,11 @@ from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.charsync import CharSync
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from milkymist.dvisampler.decoding import Decoding
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from milkymist.dvisampler.chansync import ChanSync
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from milkymist.dvisampler.syncpol import SyncPolarity
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from milkymist.dvisampler.resdetection import ResolutionDetection
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from milkymist.dvisampler.analysis import SyncPolarity, ResolutionDetection, FrameExtraction
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from milkymist.dvisampler.dma import DMA
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class DVISampler(Module, AutoCSR):
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def __init__(self, pads):
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def __init__(self, pads, asmiport):
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self.submodules.edid = EDID(pads)
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self.submodules.clocking = Clocking(pads)
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@ -54,6 +52,8 @@ class DVISampler(Module, AutoCSR):
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self.chansync.data_in2.eq(self.data2_decod.output),
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]
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###
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self.submodules.syncpol = SyncPolarity()
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self.comb += [
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self.syncpol.valid_i.eq(self.chansync.chan_synced),
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@ -64,42 +64,20 @@ class DVISampler(Module, AutoCSR):
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self.submodules.resdetection = ResolutionDetection()
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self.comb += [
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self.resdetection.valid_i.eq(self.syncpol.valid_o),
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self.resdetection.de.eq(self.syncpol.de),
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self.resdetection.vsync.eq(self.syncpol.vsync)
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]
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class RawDVISampler(Module, AutoCSR):
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def __init__(self, pads, asmiport):
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self.submodules.edid = EDID(pads)
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self.submodules.clocking = Clocking(pads)
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invert = False
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try:
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s = getattr(pads, "data0")
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except AttributeError:
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s = getattr(pads, "data0_n")
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invert = True
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self.submodules.data0_cap = DataCapture(8, invert)
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self.submodules.frame = FrameExtraction()
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self.comb += [
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self.data0_cap.pad.eq(s),
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self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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self.frame.valid_i.eq(self.syncpol.valid_o),
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self.frame.de.eq(self.syncpol.de),
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self.frame.vsync.eq(self.syncpol.vsync),
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self.frame.r.eq(self.syncpol.r),
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self.frame.g.eq(self.syncpol.g),
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self.frame.b.eq(self.syncpol.b)
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]
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fifo = AsyncFIFO(10, 1024)
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self.add_submodule(fifo, {"write": "pix", "read": "sys"})
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self.comb += [
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fifo.din.eq(self.data0_cap.d),
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fifo.we.eq(1)
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]
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pack_factor = asmiport.hub.dw//16
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self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
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self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
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self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_SINGLE_SHOT)
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self.comb += [
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self.packer.sink.stb.eq(fifo.readable),
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fifo.re.eq(self.packer.sink.ack),
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self.packer.sink.payload.word.eq(fifo.dout),
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self.packer.source.connect(self.cast.sink, match_by_position=True),
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self.cast.source.connect(self.dma.data, match_by_position=True)
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]
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self.submodules.dma = DMA(asmiport)
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self.comb += self.frame.frame.connect(self.dma.frame)
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@ -0,0 +1,148 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.record import Record
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from migen.bank.description import *
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from migen.flow.actor import *
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from milkymist.dvisampler.common import channel_layout, frame_layout
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class SyncPolarity(Module):
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def __init__(self):
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self.valid_i = Signal()
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self.data_in0 = Record(channel_layout)
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self.data_in1 = Record(channel_layout)
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self.data_in2 = Record(channel_layout)
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self.valid_o = Signal()
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self.de = Signal()
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self.hsync = Signal()
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self.vsync = Signal()
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self.r = Signal(8)
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self.g = Signal(8)
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self.b = Signal(8)
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###
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de = self.data_in0.de
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de_r = Signal()
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c = self.data_in0.c
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c_polarity = Signal(2)
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c_out = Signal(2)
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self.comb += [
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self.de.eq(de_r),
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self.hsync.eq(c_out[0]),
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self.vsync.eq(c_out[1])
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]
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self.sync.pix += [
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self.valid_o.eq(self.valid_i),
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self.r.eq(self.data_in2.d),
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self.g.eq(self.data_in1.d),
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self.b.eq(self.data_in0.d),
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de_r.eq(de),
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If(de_r & ~de,
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c_polarity.eq(c),
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c_out.eq(0)
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).Else(
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c_out.eq(c ^ c_polarity)
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)
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]
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class ResolutionDetection(Module, AutoCSR):
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def __init__(self, nbits=11):
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self.valid_i = Signal()
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self.vsync = Signal()
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self.de = Signal()
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self._hres = CSRStatus(nbits)
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self._vres = CSRStatus(nbits)
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###
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# Detect DE transitions
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de_r = Signal()
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pn_de = Signal()
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self.sync.pix += de_r.eq(self.de)
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self.comb += pn_de.eq(~self.de & de_r)
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# HRES
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hcounter = Signal(nbits)
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self.sync.pix += If(self.valid_i & self.de,
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hcounter.eq(hcounter + 1)
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).Else(
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hcounter.eq(0)
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)
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hcounter_st = Signal(nbits)
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self.sync.pix += If(self.valid_i,
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If(pn_de, hcounter_st.eq(hcounter))
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).Else(
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hcounter_st.eq(0)
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)
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self.specials += MultiReg(hcounter_st, self._hres.status)
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# VRES
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vsync_r = Signal()
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p_vsync = Signal()
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self.sync.pix += vsync_r.eq(self.vsync),
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self.comb += p_vsync.eq(self.vsync & ~vsync_r)
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vcounter = Signal(nbits)
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self.sync.pix += If(self.valid_i & p_vsync,
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vcounter.eq(0)
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).Elif(pn_de,
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vcounter.eq(vcounter + 1)
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)
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vcounter_st = Signal(nbits)
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self.sync.pix += If(self.valid_i,
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If(p_vsync, vcounter_st.eq(vcounter))
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).Else(
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vcounter_st.eq(0)
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)
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self.specials += MultiReg(vcounter_st, self._vres.status)
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class FrameExtraction(Module):
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def __init__(self):
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# in pix clock domain
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self.valid_i = Signal()
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self.vsync = Signal()
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self.de = Signal()
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self.r = Signal(8)
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self.g = Signal(8)
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self.b = Signal(8)
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# in sys clock domain
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self.frame = Source(frame_layout)
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self.busy = Signal()
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###
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fifo_stb = Signal()
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fifo_in = Record(frame_layout)
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self.comb += [
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fifo_stb.eq(self.valid_i & self.de),
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fifo_in.r.eq(self.r),
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fifo_in.g.eq(self.g),
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fifo_in.b.eq(self.b),
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]
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vsync_r = Signal()
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self.sync.pix += [
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If(self.vsync & ~vsync_r, fifo_in.parity.eq(~fifo_in.parity)),
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vsync_r.eq(self.vsync)
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]
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fifo = AsyncFIFO(layout_len(frame_layout), 256)
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self.add_submodule(fifo, {"write": "pix", "read": "sys"})
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self.comb += [
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fifo.we.eq(fifo_stb),
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fifo.din.eq(fifo_in.raw_bits()),
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self.frame.stb.eq(fifo.readable),
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self.frame.payload.raw_bits().eq(fifo.dout),
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fifo.re.eq(self.frame.ack),
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self.busy.eq(0)
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]
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@ -1,2 +1,3 @@
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control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
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channel_layout = [("d", 8), ("c", 2), ("de", 1)]
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frame_layout = [("parity", 1), ("r", 8), ("g", 8), ("b", 8)]
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@ -0,0 +1,46 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.record import layout_len
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from migen.bank.description import AutoCSR
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from migen.actorlib import structuring, dma_asmi, spi
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.datacapture import DataCapture
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class RawDVISampler(Module, AutoCSR):
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def __init__(self, pads, asmiport):
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self.submodules.edid = EDID(pads)
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self.submodules.clocking = Clocking(pads)
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invert = False
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try:
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s = getattr(pads, "data0")
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except AttributeError:
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s = getattr(pads, "data0_n")
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invert = True
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self.submodules.data0_cap = DataCapture(8, invert)
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self.comb += [
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self.data0_cap.pad.eq(s),
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self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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]
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fifo = AsyncFIFO(10, 256)
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self.add_submodule(fifo, {"write": "pix", "read": "sys"})
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self.comb += [
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fifo.din.eq(self.data0_cap.d),
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fifo.we.eq(1)
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]
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pack_factor = asmiport.hub.dw//16
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self.submodules.packer = structuring.Pack([("word", 10), ("pad", 6)], pack_factor)
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self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw)
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self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_SINGLE_SHOT, free_flow=True)
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self.comb += [
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self.packer.sink.stb.eq(fifo.readable),
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fifo.re.eq(self.packer.sink.ack),
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self.packer.sink.payload.word.eq(fifo.dout),
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self.packer.source.connect(self.cast.sink, match_by_position=True),
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self.cast.source.connect(self.dma.data, match_by_position=True)
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]
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@ -0,0 +1,48 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.bank.description import *
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from migen.flow.actor import *
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from migen.actorlib import structuring, dma_asmi, spi
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from milkymist.dvisampler.common import frame_layout
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class DMA(Module):
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def __init__(self, asmiport):
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self.frame = Sink(frame_layout)
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self.shoot = CSR()
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###
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sof = Signal()
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parity_r = Signal()
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self.comb += sof.eq(self.frame.stb & (parity_r ^ self.frame.payload.parity))
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self.sync += If(self.frame.stb & self.frame.ack, parity_r.eq(self.frame.payload.parity))
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pending = Signal()
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frame_en = Signal()
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self.sync += [
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If(sof,
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frame_en.eq(0),
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If(pending, frame_en.eq(1)),
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pending.eq(0)
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),
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If(self.shoot.re, pending.eq(1))
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]
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pack_factor = asmiport.hub.dw//32
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self.submodules.packer = structuring.Pack(list(reversed([("pad", 2), ("r", 10), ("g", 10), ("b", 10)])), pack_factor)
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self.submodules.cast = structuring.Cast(self.packer.source.payload.layout, asmiport.hub.dw, reverse_from=False)
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self.submodules.dma = spi.DMAWriteController(dma_asmi.Writer(asmiport), spi.MODE_EXTERNAL)
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self.comb += [
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self.dma.generator.trigger.eq(self.shoot.re),
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self.packer.sink.stb.eq(self.frame.stb & frame_en),
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self.frame.ack.eq(self.packer.sink.ack | (~frame_en & ~(pending & sof))),
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self.packer.sink.payload.r.eq(self.frame.payload.r << 2),
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self.packer.sink.payload.g.eq(self.frame.payload.g << 2),
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self.packer.sink.payload.b.eq(self.frame.payload.b << 2),
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self.packer.source.connect(self.cast.sink, match_by_position=True),
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self.cast.source.connect(self.dma.data, match_by_position=True)
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]
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def get_csrs(self):
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return [self.shoot] + self.dma.get_csrs()
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@ -1,49 +0,0 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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class ResolutionDetection(Module, AutoCSR):
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def __init__(self, nbits=11):
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self.vsync = Signal()
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self.de = Signal()
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self._hres = CSRStatus(nbits)
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self._vres = CSRStatus(nbits)
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###
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# Detect DE transitions
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de_r = Signal()
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pn_de = Signal()
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self.sync.pix += de_r.eq(self.de)
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self.comb += pn_de.eq(~self.de & de_r)
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# HRES
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hcounter = Signal(nbits)
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self.sync.pix += If(self.de,
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hcounter.eq(hcounter + 1)
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).Else(
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hcounter.eq(0)
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)
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hcounter_st = Signal(nbits)
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self.sync.pix += If(pn_de, hcounter_st.eq(hcounter))
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self.specials += MultiReg(hcounter_st, self._hres.status)
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# VRES
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vsync_r = Signal()
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p_vsync = Signal()
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self.sync.pix += vsync_r.eq(self.vsync),
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self.comb += p_vsync.eq(self.vsync & ~vsync_r)
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vcounter = Signal(nbits)
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self.sync.pix += If(p_vsync,
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vcounter.eq(0)
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).Elif(pn_de,
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vcounter.eq(vcounter + 1)
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)
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vcounter_st = Signal(nbits)
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self.sync.pix += If(p_vsync, vcounter_st.eq(vcounter))
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self.specials += MultiReg(vcounter_st, self._vres.status)
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@ -1,49 +0,0 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.record import Record
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from milkymist.dvisampler.common import channel_layout
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class SyncPolarity(Module):
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def __init__(self):
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self.valid_i = Signal()
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self.data_in0 = Record(channel_layout)
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self.data_in1 = Record(channel_layout)
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self.data_in2 = Record(channel_layout)
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self.valid_o = Signal()
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self.de = Signal()
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self.hsync = Signal()
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self.vsync = Signal()
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self.r = Signal(8)
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self.g = Signal(8)
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self.b = Signal(8)
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###
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de = self.data_in0.de
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de_r = Signal()
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c = self.data_in0.c
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c_polarity = Signal(2)
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c_out = Signal(2)
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self.comb += [
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self.de.eq(de_r),
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self.hsync.eq(c_out[0]),
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self.vsync.eq(c_out[1])
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]
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self.sync.pix += [
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self.valid_o.eq(self.valid_i),
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self.r.eq(self.data_in2.d),
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self.g.eq(self.data_in1.d),
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self.b.eq(self.data_in0.d),
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de_r.eq(de),
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If(de_r & ~de,
|
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c_polarity.eq(c),
|
||||
c_out.eq(0)
|
||||
).Else(
|
||||
c_out.eq(c ^ c_polarity)
|
||||
)
|
||||
]
|
||||
5
top.py
5
top.py
|
|
@ -92,6 +92,7 @@ class SoC(Module):
|
|||
self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
|
||||
asmiport_wb = self.asmicon.hub.get_port()
|
||||
asmiport_fb = self.asmicon.hub.get_port(3)
|
||||
asmiport_dvi0 = self.asmicon.hub.get_port(2)
|
||||
self.asmicon.finalize()
|
||||
|
||||
#
|
||||
|
|
@ -141,8 +142,8 @@ class SoC(Module):
|
|||
self.submodules.timer0 = timer.Timer()
|
||||
self.submodules.fb = framebuffer.Framebuffer(platform.request("vga"), asmiport_fb)
|
||||
self.submodules.asmiprobe = asmiprobe.ASMIprobe(self.asmicon.hub)
|
||||
self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0))
|
||||
self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1))
|
||||
self.submodules.dvisampler0 = dvisampler.DVISampler(platform.request("dvi_in", 0), asmiport_dvi0)
|
||||
#self.submodules.dvisampler1 = dvisampler.DVISampler(platform.request("dvi_in", 1))
|
||||
|
||||
self.submodules.csrbankarray = csrgen.BankArray(self,
|
||||
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
|
||||
|
|
|
|||
Loading…
Reference in New Issue