litex/misoclib/mem/litesata/example_designs/test/test_regs.py

def main(wb):
	wb.open()
	regs = wb.regs
	###
	print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
	print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
	print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
	###
	wb.close()
liteXXX cores: share same methodology for on-board tests 2015-03-01 05:07:28 -05:00			`def main(wb):`
			`wb.open()`
			`regs = wb.regs`
			`###`
LiteXXX cores: use format in prints 2015-03-03 04:29:28 -05:00			`print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))`
			`print("revision : 0x{:04x}".format(regs.identifier_revision.read()))`
LiteXXX cores: fix frequency print in test/test_regs.py 2015-03-17 11:01:12 -04:00			`print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))`
liteXXX cores: share same methodology for on-board tests 2015-03-01 05:07:28 -05:00			`###`
			`wb.close()`