litex/misoclib/mem/litesata/example_designs/test/test_regs.py

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def main(wb):
wb.open()
regs = wb.regs
###
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print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
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print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
###
wb.close()