2013-04-08 14:28:23 -04:00
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from mibuild.generic_platform import *
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from mibuild.xilinx_ise import XilinxISEPlatform, CRG_SE
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_io = [
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("user_led", 0, Pins("P112"), IOStandard("LVCMOS33"), Drive(24), Misc("SLEW=QUIETIO")),
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("user_btn", 0, Pins("P114"), IOStandard("LVCMOS33")), # C0
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("user_btn", 1, Pins("P115"), IOStandard("LVCMOS33")), # C1
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("clk32", 0, Pins("P94"), IOStandard("LVCMOS33")),
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("serial", 0,
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2013-05-19 14:24:47 -04:00
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Subsignal("tx", Pins("P105"), IOStandard("LVCMOS33"), Misc("SLEW=SLOW")),
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Subsignal("rx", Pins("P101"), IOStandard("LVCMOS33"), Misc("PULLUP"))
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2013-04-08 14:28:23 -04:00
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),
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("spiflash", 0,
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Subsignal("cs", Pins("P38")),
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Subsignal("clk", Pins("P70")),
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Subsignal("mosi", Pins("P64")),
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Subsignal("miso", Pins("P65"), Misc("PULLUP")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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("sdram_clock", 0, Pins("P32"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
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("sdram", 0,
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Subsignal("a", Pins("P140", "P139", "P138", "P137", "P46", "P45", "P44",
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"P43", "P41", "P40", "P141", "P35", "P34")),
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Subsignal("ba", Pins("P143", "P142")),
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Subsignal("cs_n", Pins("P1")),
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Subsignal("cke", Pins("P33")),
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Subsignal("ras_n", Pins("P2")),
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Subsignal("cas_n", Pins("P5")),
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Subsignal("we_n", Pins("P6")),
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Subsignal("dq", Pins("P9", "P10", "P11", "P12", "P14", "P15", "P16", "P8",
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"P21", "P22", "P23", "P24", "P26", "P27", "P29", "P30")),
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Subsignal("dm", Pins("P7", "P17")),
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IOStandard("LVCMOS33"), Misc("SLEW=FAST")
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),
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]
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class Platform(XilinxISEPlatform):
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def __init__(self):
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XilinxISEPlatform.__init__(self, "xc6slx9-tqg144-2", _io,
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2013-05-07 13:10:18 -04:00
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lambda p: CRG_SE(p, "clk32", None, 31.25))
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