Sebastien Bourdeauducq 953e603915 xilinx_ise: improve parameter passing		2013-06-01 17:22:57 +02:00
..
platforms	platform/rhino: rename ismm data out signal to locked	2013-05-30 11:06:02 +02:00
__init__.py	Initial version	2013-02-07 22:07:30 +01:00
altera_quartus.py	altera_quartus: fix clock domain name	2013-03-26 23:05:46 +01:00
crg.py	Use migen.fhdl.std	2013-05-26 18:07:26 +02:00
generic_platform.py	Use migen.fhdl.std	2013-05-26 18:07:26 +02:00
tools.py	Support adding Verilog/VHDL files	2013-02-08 20:25:20 +01:00
xilinx_ise.py	xilinx_ise: improve parameter passing	2013-06-01 17:22:57 +02:00