34 lines
1.2 KiB
Python
34 lines
1.2 KiB
Python
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from mibuild.generic_platform import *
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from mibuild.xilinx_ise import XilinxISEPlatform
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_io = [
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("epb", 0,
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Subsignal("cs_n", Pins("K13")),
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Subsignal("r_w_n", Pins("AF20")),
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Subsignal("be_n", Pins("AF14", "AF18")),
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Subsignal("oe_n", Pins("AF21")),
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Subsignal("addr", Pins("AE23", "AE22", "AG18", "AG12", "AG15", "AG23", "AF19", "AE12", "AG16", "AF13", "AG20", "AF23",
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"AH17", "AH15", "L20", "J22", "H22", "L15", "L16", "K22", "K21", "K16", "J15")),
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Subsignal("addr_gp", Pins("L21", "G22", "K23", "K14", "L14", "J12")),
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Subsignal("data", Pins("AF15", "AE16", "AE21", "AD20", "AF16", "AE17", "AE19", "AD19", "AG22", "AH22", "AH12", "AG13",
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"AH20", "AH19", "AH14", "AH13")),
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Subsignal("rdy", Pins("K12")),
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IOStandard("LVCMOS33")
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),
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("roach_clocks", 0,
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Subsignal("epb_clk", Pins("AH18"), IOStandard("LVCMOS33")),
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Subsignal("sys_clk_n", Pins("H13")),
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Subsignal("sys_clk_p", Pins("J14")),
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Subsignal("aux0_clk_p", Pins("G15")),
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Subsignal("aux0_clk_n", Pins("G16")),
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Subsignal("aux1_clk_p", Pins("H14")),
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Subsignal("aux1_clk_n", Pins("H15")),
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Subsignal("dly_clk_n", Pins("J17")),
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Subsignal("dly_clk_p", Pins("J16")),
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),
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]
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class Platform(XilinxISEPlatform):
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def __init__(self):
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XilinxISEPlatform.__init__(self, "xc5vsx95t-ff1136-1", _io)
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