litex/liteeth/test/mac_core_tb.py

59 lines
2.0 KiB
Python
Raw Normal View History

2015-01-27 17:59:06 -05:00
from migen.fhdl.std import *
from migen.bus import wishbone
from migen.bus.transactions import *
from migen.sim.generic import run_simulation
2015-01-28 13:07:59 -05:00
from liteeth.common import *
from liteeth.mac import LiteEthMAC
2015-01-27 17:59:06 -05:00
2015-01-28 13:07:59 -05:00
from liteeth.test.common import *
from liteeth.test.model import phy, mac
2015-01-27 17:59:06 -05:00
class TB(Module):
def __init__(self):
2015-01-28 14:44:41 -05:00
self.submodules.hostphy = phy.PHY(8, debug=False)
self.submodules.hostmac = mac.MAC(self.hostphy, debug=False, loopback=True)
2015-01-28 13:07:59 -05:00
self.submodules.ethmac = LiteEthMAC(phy=self.hostphy, dw=32, interface="core", with_hw_preamble_crc=True)
self.submodules.streamer = PacketStreamer(eth_mac_description(32), last_be=1)
2015-01-28 14:44:41 -05:00
self.submodules.streamer_randomizer = AckRandomizer(eth_mac_description(32), level=50)
2015-01-28 13:07:59 -05:00
2015-01-28 14:44:41 -05:00
self.submodules.logger_randomizer = AckRandomizer(eth_mac_description(32), level=50)
2015-01-28 13:07:59 -05:00
self.submodules.logger = PacketLogger(eth_mac_description(32))
2015-01-27 17:59:06 -05:00
# use sys_clk for each clock_domain
self.clock_domains.cd_eth_rx = ClockDomain()
self.clock_domains.cd_eth_tx = ClockDomain()
self.comb += [
self.cd_eth_rx.clk.eq(ClockSignal()),
self.cd_eth_rx.rst.eq(ResetSignal()),
self.cd_eth_tx.clk.eq(ClockSignal()),
self.cd_eth_tx.rst.eq(ResetSignal()),
]
2015-01-28 13:07:59 -05:00
self.comb += [
Record.connect(self.streamer.source, self.streamer_randomizer.sink),
Record.connect(self.streamer_randomizer.source, self.ethmac.sink),
Record.connect(self.ethmac.source, self.logger_randomizer.sink),
Record.connect(self.logger_randomizer.source, self.logger.sink)
]
2015-01-27 17:59:06 -05:00
def gen_simulation(self, selfp):
selfp.cd_eth_rx.rst = 1
selfp.cd_eth_tx.rst = 1
yield
selfp.cd_eth_rx.rst = 0
selfp.cd_eth_tx.rst = 0
2015-01-28 13:07:59 -05:00
for i in range(8):
streamer_packet = Packet([i for i in range(64)])
yield from self.streamer.send(streamer_packet)
2015-01-28 14:44:41 -05:00
yield from self.logger.receive()
# check results
s, l, e = check(streamer_packet, self.logger.packet)
print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
2015-01-27 17:59:06 -05:00
if __name__ == "__main__":
2015-01-28 14:44:41 -05:00
run_simulation(TB(), ncycles=4000, vcd_name="my.vcd", keep_files=True)