2013-05-22 11:10:13 -04:00
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from migen.fhdl.std import *
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2013-05-10 15:03:55 -04:00
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from migen.flow.actor import *
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2012-06-17 11:22:02 -04:00
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from migen.flow.network import *
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2013-05-10 15:03:55 -04:00
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from migen.bank.description import CSRStorage, AutoCSR
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2013-06-11 08:18:16 -04:00
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from migen.actorlib import dma_lasmi, structuring, sim, spi
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2012-06-17 11:22:02 -04:00
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2013-05-09 13:23:22 -04:00
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from milkymist.framebuffer.lib import bpp, pixel_layout, dac_layout, FrameInitiator, VTG, FIFO
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2012-07-03 13:04:44 -04:00
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2013-03-10 14:32:38 -04:00
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class Framebuffer(Module):
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def __init__(self, pads, lasmim, simulation=False):
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pack_factor = lasmim.dw//(2*bpp)
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2013-05-09 13:23:22 -04:00
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packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
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2012-06-17 12:36:23 -04:00
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2013-05-09 13:23:22 -04:00
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fi = FrameInitiator()
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2013-06-11 08:18:16 -04:00
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dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4)
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cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True)
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2013-05-09 13:23:22 -04:00
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unpack = structuring.Unpack(pack_factor, pixel_layout)
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2012-12-12 16:52:55 -05:00
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vtg = VTG()
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2012-07-03 13:04:44 -04:00
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if simulation:
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fifo = sim.SimActor(sim_fifo_gen(), ("dac", Sink, dac_layout))
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2012-07-03 13:04:44 -04:00
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else:
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fifo = FIFO()
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2012-06-17 11:22:02 -04:00
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2012-06-17 12:36:23 -04:00
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g = DataFlowGraph()
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2013-04-30 12:55:35 -04:00
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g.add_connection(fi, vtg, sink_ep="timing")
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g.add_connection(dma, cast)
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2012-06-29 10:11:05 -04:00
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g.add_connection(cast, unpack)
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2012-06-29 11:09:16 -04:00
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g.add_connection(unpack, vtg, sink_ep="pixels")
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g.add_connection(vtg, fifo)
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2013-04-30 12:55:35 -04:00
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self.submodules += CompositeActor(g)
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self._enable = CSRStorage()
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self.comb += [
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fi.trigger.eq(self._enable.storage),
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dma.generator.trigger.eq(self._enable.storage),
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]
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self._fi = fi
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self._dma = dma
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2012-06-17 11:22:02 -04:00
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2013-03-26 12:57:17 -04:00
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# Drive pads
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if not simulation:
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2013-03-26 12:57:17 -04:00
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self.comb += [
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pads.hsync_n.eq(fifo.vga_hsync_n),
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pads.vsync_n.eq(fifo.vga_vsync_n),
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pads.r.eq(fifo.vga_r),
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pads.g.eq(fifo.vga_g),
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pads.b.eq(fifo.vga_b)
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]
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self.comb += pads.psave_n.eq(1)
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2013-03-10 14:32:38 -04:00
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2013-03-30 12:28:15 -04:00
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def get_csrs(self):
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return [self._enable] + self._fi.get_csrs() + self._dma.get_csrs()
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class Blender(PipelinedActor, AutoCSR):
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def __init__(self, nimages, latency):
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sink_layout = [("i"+str(i), pixel_layout) for i in range(nimages)]
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self.sink = Sink(sink_layout)
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self.source = Source(pixel_layout)
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factors = []
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for i in range(nimages):
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name = "f"+str(i)
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csr = CSRStorage(8, name=name)
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setattr(self, name, csr)
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factors.append(csr.storage)
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PipelinedActor.__init__(self, latency)
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###
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2013-06-13 03:41:17 -04:00
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sink_registered = Record(sink_layout)
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self.sync += If(self.pipe_ce, sink_registered.eq(self.sink.payload))
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imgs = [getattr(sink_registered, "i"+str(i)) for i in range(nimages)]
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outval = Record(pixel_layout)
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for e in pixel_layout:
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name = e[0]
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inpixs = [getattr(img, name) for img in imgs]
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outpix = getattr(outval, name)
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for component in ["r", "g", "b"]:
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incomps = [getattr(pix, component) for pix in inpixs]
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outcomp = getattr(outpix, component)
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2013-05-16 11:45:21 -04:00
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outcomp_full = Signal(19)
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2013-05-11 03:21:12 -04:00
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self.comb += [
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outcomp_full.eq(sum(incomp*factor for incomp, factor in zip(incomps, factors))),
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If(outcomp_full[18],
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outcomp.eq(2**10 - 1) # saturate on overflow
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).Else(
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outcomp.eq(outcomp_full[8:18])
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)
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]
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pipe_stmts = []
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for i in range(latency-1):
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new_outval = Record(pixel_layout)
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pipe_stmts.append(new_outval.eq(outval))
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outval = new_outval
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self.sync += If(self.pipe_ce, pipe_stmts)
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self.comb += self.source.payload.eq(outval)
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class MixFramebuffer(Module, AutoCSR):
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2013-06-11 08:18:16 -04:00
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def __init__(self, pads, *lasmims, blender_latency=5):
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pack_factor = lasmims[0].dw//(2*bpp)
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packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
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self._enable = CSRStorage()
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self.fi = FrameInitiator()
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self.blender = Blender(len(lasmims), blender_latency)
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self.comb += self.fi.trigger.eq(self._enable.storage)
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g = DataFlowGraph()
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2013-06-11 08:18:16 -04:00
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for n, lasmim in enumerate(lasmims):
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dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4)
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cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True)
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unpack = structuring.Unpack(pack_factor, pixel_layout)
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g.add_connection(dma, cast)
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g.add_connection(cast, unpack)
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2013-05-11 03:21:12 -04:00
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g.add_connection(unpack, self.blender, sink_subr=["i"+str(n)])
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2013-05-10 15:03:55 -04:00
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self.comb += dma.generator.trigger.eq(self._enable.storage)
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setattr(self, "dma"+str(n), dma)
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vtg = VTG()
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fifo = FIFO()
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g.add_connection(self.fi, vtg, sink_ep="timing")
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g.add_connection(self.blender, vtg, sink_ep="pixels")
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g.add_connection(vtg, fifo)
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self.submodules += CompositeActor(g)
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self.comb += [
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pads.hsync_n.eq(fifo.vga_hsync_n),
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pads.vsync_n.eq(fifo.vga_vsync_n),
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pads.r.eq(fifo.vga_r),
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pads.g.eq(fifo.vga_g),
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pads.b.eq(fifo.vga_b),
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pads.psave_n.eq(1)
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]
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