61 lines
2.0 KiB
Python
61 lines
2.0 KiB
Python
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.fhdl.specials import Instance
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from migen.genlib.cdc import MultiReg
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from migen.bank.description import *
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class Clocking(Module, AutoReg):
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def __init__(self):
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self.clkin = Signal()
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self._r_pll_reset = RegisterField(reset=1)
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self._r_locked = RegisterField(1, READ_ONLY, WRITE_ONLY)
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self.locked = Signal()
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self.serdesstrobe = Signal()
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self._cd_pix = ClockDomain()
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self._cd_pix5x = ClockDomain()
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self._cd_pix20x = ClockDomain()
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###
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clkfbout = Signal()
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pll_locked = Signal()
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pll_clk0 = Signal()
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pll_clk1 = Signal()
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pll_clk2 = Signal()
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self.specials += Instance("PLL_BASE",
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Instance.Parameter("CLKIN_PERIOD", 22.0),
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Instance.Parameter("CLKFBOUT_MULT", 20),
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Instance.Parameter("CLKOUT0_DIVIDE", 20), # pix
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Instance.Parameter("CLKOUT1_DIVIDE", 4), # pix5x
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Instance.Parameter("CLKOUT2_DIVIDE", 1), # pix20x
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Instance.Parameter("COMPENSATION", "INTERNAL"),
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Instance.Output("CLKFBOUT", clkfbout),
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Instance.Output("CLKOUT0", pll_clk0),
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Instance.Output("CLKOUT1", pll_clk1),
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Instance.Output("CLKOUT2", pll_clk2),
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Instance.Output("LOCKED", pll_locked),
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Instance.Input("CLKFBIN", clkfbout),
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Instance.Input("CLKIN", self.clkin),
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Instance.Input("RST", self._r_pll_reset.field.r)
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)
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self.specials += Instance("BUFG",
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Instance.Input("I", pll_clk0), Instance.Output("O", self._cd_pix.clk))
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self.specials += Instance("BUFG",
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Instance.Input("I", pll_clk1), Instance.Output("O", self._cd_pix5x.clk))
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locked_async = Signal()
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self.specials += Instance("BUFPLL",
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Instance.Parameter("DIVIDE", 4),
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Instance.Input("PLLIN", pll_clk2),
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Instance.ClockPort("GCLK", "pix5x"),
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Instance.Input("LOCKED", pll_locked),
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Instance.Output("IOCLK", self._cd_pix20x.clk),
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Instance.Output("LOCK", locked_async),
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Instance.Output("SERDESSTROBE", self.serdesstrobe)
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)
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self.specials += MultiReg(locked_async, self.locked, "sys")
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self.comb += self._r_locked.field.w.eq(self.locked)
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