litex/examples/sim/basic1.py

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from migen import *
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# Our simple counter, which increments at every cycle.
class Counter(Module):
def __init__(self):
self.count = Signal(4)
# At each cycle, increase the value of the count signal.
# We do it with convertible/synthesizable FHDL code.
self.sync += self.count.eq(self.count + 1)
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# Simply read the count signal and print it.
# The output is:
# Count: 0
# Count: 1
# Count: 2
# ...
def counter_test(dut):
for i in range(20):
print((yield dut.count)) # read and print
yield # next clock cycle
# simulation ends with this generator
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if __name__ == "__main__":
dut = Counter()
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run_simulation(dut, counter_test(dut), vcd_name="basic1.vcd")