litex/migen/build/lattice/common.py

42 lines
1.1 KiB
Python
Raw Normal View History

from migen.fhdl.std import *
from migen.genlib.io import *
from migen.genlib.resetsync import AsyncResetSynchronizer
2015-04-13 14:45:35 -04:00
class LatticeAsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset):
rst1 = Signal()
self.specials += [
Instance("FD1S3BX", i_D=0, i_PD=async_reset,
i_CK=cd.clk, o_Q=rst1),
Instance("FD1S3BX", i_D=rst1, i_PD=async_reset,
i_CK=cd.clk, o_Q=cd.rst)
]
2015-04-13 14:45:35 -04:00
class LatticeAsyncResetSynchronizer:
@staticmethod
def lower(dr):
return LatticeAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
2015-04-13 14:45:35 -04:00
class LatticeDDROutputImpl(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDRXD1",
synthesis_directive="ODDRAPPS=\"SCLK_ALIGNED\"",
i_SCLK=clk,
i_DA=i1, i_DB=i2, o_Q=o,
)
2015-04-13 14:45:35 -04:00
2015-03-17 04:40:25 -04:00
class LatticeDDROutput:
@staticmethod
def lower(dr):
return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
2015-03-17 04:40:25 -04:00
lattice_special_overrides = {
AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
DDROutput: LatticeDDROutput
}