2013-12-08 22:23:21 -05:00
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import unittest
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from migen.fhdl.std import *
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2015-09-12 04:28:21 -04:00
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from migen.test.support import SimCase
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2013-12-08 22:23:21 -05:00
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2015-04-13 14:45:35 -04:00
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2013-12-08 22:23:21 -05:00
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class SignedCase(SimCase, unittest.TestCase):
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2015-09-12 04:28:21 -04:00
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class TestBench(Module):
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2015-04-13 14:07:07 -04:00
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def __init__(self):
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self.a = Signal((3, True))
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self.b = Signal((4, True))
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comps = [
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lambda p, q: p > q,
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lambda p, q: p >= q,
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lambda p, q: p < q,
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lambda p, q: p <= q,
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lambda p, q: p == q,
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lambda p, q: p != q,
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]
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self.vals = []
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for asign in 1, -1:
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for bsign in 1, -1:
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for f in comps:
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r = Signal()
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r0 = f(asign*self.a, bsign*self.b)
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self.comb += r.eq(r0)
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self.vals.append((asign, bsign, f, r, r0.op))
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2013-12-08 22:23:21 -05:00
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2015-04-13 14:07:07 -04:00
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def test_comparisons(self):
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2015-09-12 04:28:21 -04:00
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def gen():
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for i in range(-4, 4):
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yield self.tb.a, i
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yield self.tb.b, i
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a = yield self.tb.a
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b = yield self.tb.b
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for asign, bsign, f, r, op in self.tb.vals:
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r, r0 = (yield r), f(asign*a, bsign*b)
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self.assertEqual(r, int(r0),
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"got {}, want {}*{} {} {}*{} = {}".format(
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r, asign, a, op, bsign, b, r0))
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yield
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self.run_with(gen())
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