2011-12-16 15:30:22 -05:00
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from migen.fhdl.structure import *
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2011-12-13 11:33:12 -05:00
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from migen.bus import wishbone
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from migen.corelogic import timeline
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2012-01-21 06:25:22 -05:00
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class NorFlash:
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2011-12-13 11:33:12 -05:00
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def __init__(self, adr_width, rd_timing):
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2012-02-15 10:55:13 -05:00
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self.bus = wishbone.Interface()
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2011-12-18 16:02:05 -05:00
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self.adr = Signal(BV(adr_width-1))
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self.d = Signal(BV(16))
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self.oe_n = Signal()
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self.we_n = Signal()
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self.ce_n = Signal()
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2012-02-15 10:55:13 -05:00
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self.timeline = timeline.Timeline(self.bus.cyc & self.bus.stb,
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[(0, [self.adr.eq(Cat(0, self.bus.adr[:adr_width-2]))]),
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2011-12-13 11:33:12 -05:00
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(rd_timing, [
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2012-02-15 10:55:13 -05:00
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self.bus.dat_r[16:].eq(self.d),
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self.adr.eq(Cat(1, self.bus.adr[:adr_width-2]))]),
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2011-12-13 11:33:12 -05:00
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(2*rd_timing, [
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2012-02-15 10:55:13 -05:00
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self.bus.dat_r[:16].eq(self.d),
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self.bus.ack.eq(1)]),
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2011-12-13 11:33:12 -05:00
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(2*rd_timing+1, [
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2012-02-15 10:55:13 -05:00
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self.bus.ack.eq(0)])])
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2011-12-13 11:33:12 -05:00
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2011-12-16 10:02:49 -05:00
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def get_fragment(self):
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2011-12-16 15:30:22 -05:00
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comb = [self.oe_n.eq(0), self.we_n.eq(1),
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2011-12-16 16:25:26 -05:00
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self.ce_n.eq(0)]
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return Fragment(comb, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n}) \
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2011-12-16 10:02:49 -05:00
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+ self.timeline.get_fragment()
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