litex/CHANGES

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[> 2020.XX, planned for July 2020
---------------------------------
[> Issues resolved
------------------
2020-05-04 03:59:01 -04:00
- Fix flush_cpu_icache on VexRiscv.
[> Added Features
------------------
2020-05-14 03:34:37 -04:00
- Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
- Improve WishboneBridge.
- Improve Diamond constraints.
- Add LedChaser on boards.
- Speedup Memtest using an LFSR.
- Add Microwatt CPU support.
- Improve boards's programmers.
2020-05-04 03:59:01 -04:00
- BIOS history, autocomplete.
- Pluggable CPUs.
2020-05-01 14:13:05 -04:00
- Add nMigen dependency.
- Properly integrate Minerva CPU.
[> API changes/Deprecation
--------------------------
2020-05-14 03:34:37 -04:00
- Add --build --load arguments to targets.
[> 2020.04, released April 28th, 2020
-------------------------------------
[> Description
--------------
First release of LiteX and the ecosystem of cores!
LiteX is a Migen/MiSoC based Core/SoC builder that provides the infrastructure to easily create
Cores/SoCs (with or without CPU).
The common components of a SoC are provided directly:
- Buses and Streams (Wishbone, AXI, Avalon-ST)
- Interconnect
- Common cores (RAM, ROM, Timer, UART, etc...)
- CPU wrappers/integration
- etc...
And SoC creation capabilities can be greatly extended with the ecosystem of LiteX cores (DRAM,
PCIe, Ethernet, SATA, etc...) that can be integrated/simulated/build easily with LiteX.
It also provides build backends for open-source and vendors toolchains.
[> Issues resolved
------------------
- NA
[> Added Features
------------------
- NA
[> API changes/Deprecation
--------------------------
- https://github.com/enjoy-digital/litex/pull/399: Converting LiteX to use Python modules.