litex/tb/asmicon/asmicon.py

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from migen.fhdl.structure import *
from migen.bus.asmibus import *
from migen.sim.generic import Simulator, TopLevel
from milkymist.asmicon import *
from common import sdram_phy, sdram_geom, sdram_timing, DFILogger
def my_generator_r():
for x in range(50):
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t = TRead(x)
yield t
print("reads done")
def my_generator_w():
for x in range(50):
t = TWrite(x, x)
yield t
print("writes done")
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def main():
dut = ASMIcon(sdram_phy, sdram_geom, sdram_timing)
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initiator1 = Initiator(my_generator_r(), dut.hub.get_port())
initiator2 = Initiator(my_generator_w(), dut.hub.get_port())
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dut.finalize()
logger = DFILogger(dut.dfi)
def end_simulation(s):
s.interrupt = initiator1.done and initiator2.done
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fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \
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logger.get_fragment() + \
Fragment(sim=[end_simulation])
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sim = Simulator(fragment, TopLevel("my.vcd"))
sim.run(700)
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main()