tb: use default runner
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parent
a94ee3884f
commit
f68fcef90c
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@ -1,7 +1,6 @@
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from migen.fhdl.structure import *
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from migen.bus.asmibus import *
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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from milkymist.asmicon import *
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@ -33,7 +32,7 @@ def main():
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fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \
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logger.get_fragment() + \
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Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
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sim = Simulator(fragment, TopLevel("my.vcd"))
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sim.run(700)
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main()
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@ -1,7 +1,6 @@
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from migen.fhdl.structure import *
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from migen.bus import wishbone, wishbone2asmi, asmibus
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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from milkymist.asmicon import *
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@ -41,7 +40,7 @@ def main():
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conn.get_fragment() + \
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logger.get_fragment() + \
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Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
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sim = Simulator(fragment, TopLevel("my.vcd"))
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sim.run()
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main()
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@ -1,7 +1,6 @@
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from migen.fhdl.structure import *
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from migen.bus.asmibus import *
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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from milkymist.asmicon.bankmachine import *
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@ -42,7 +41,7 @@ def main():
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fragment = hub.get_fragment() + initiator.get_fragment() + \
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dut.get_fragment() + logger.get_fragment() + completer.get_fragment() + \
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Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
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sim = Simulator(fragment, TopLevel("my.vcd"))
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sim.run()
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main()
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@ -2,7 +2,6 @@ from random import Random
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from migen.fhdl.structure import *
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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from milkymist.asmicon.refresher import *
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@ -44,7 +43,7 @@ def main():
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logger = CommandLogger(dut.cmd)
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granter = Granter(dut.req, dut.ack)
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fragment = dut.get_fragment() + logger.get_fragment() + granter.get_fragment()
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sim = Simulator(fragment, Runner())
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sim = Simulator(fragment)
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sim.run(400)
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main()
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@ -3,7 +3,6 @@ from random import Random
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from migen.fhdl.structure import *
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from migen.bus.asmibus import *
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from migen.sim.generic import Simulator, TopLevel
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from migen.sim.icarus import Runner
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from milkymist.asmicon.bankmachine import _AddressSlicer, _SimpleSelector
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@ -71,7 +70,7 @@ def main():
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fragment = hub.get_fragment() + sum([i.get_fragment() for i in initiators], Fragment()) + \
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logger.get_fragment() + selector.get_fragment() + completer.get_fragment() + \
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Fragment(sim=[end_simulation])
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sim = Simulator(fragment, Runner(), TopLevel("my.vcd"))
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sim = Simulator(fragment, TopLevel("my.vcd"))
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sim.run()
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main()
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@ -1,7 +1,6 @@
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from migen.fhdl.structure import *
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from migen.bus import asmibus
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from migen.sim.generic import Simulator
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from migen.sim.icarus import Runner
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from milkymist.framebuffer import *
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@ -13,7 +12,7 @@ def main():
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dut = Framebuffer(1, port, True)
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fragment = hub.get_fragment() + dut.get_fragment()
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sim = Simulator(fragment, Runner())
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sim = Simulator(fragment)
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sim.run(1)
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def csr_w(addr, d):
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