2015-11-07 06:26:46 -05:00
|
|
|
__ _ __ _ __
|
|
|
|
/ / (_) /____ | |/_/
|
|
|
|
/ /__/ / __/ -_)> <
|
|
|
|
/____/_/\__/\__/_/|_|
|
2015-11-11 06:10:55 -05:00
|
|
|
Migen inside
|
2015-11-07 06:26:46 -05:00
|
|
|
|
|
|
|
Build your hardware, easily!
|
2015-11-11 07:15:54 -05:00
|
|
|
Copyright 2012-2015 Enjoy-Digital
|
2015-11-07 06:26:46 -05:00
|
|
|
|
|
|
|
[> Intro
|
|
|
|
---------
|
2015-11-11 06:10:55 -05:00
|
|
|
LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
|
|
|
|
our cores, integrate them in complete SoC and load/flash them to the hardware.
|
2015-11-07 06:26:46 -05:00
|
|
|
|
2015-11-11 06:10:55 -05:00
|
|
|
The structure of LiteX is kept close to MiSoC to ease collaboration between
|
|
|
|
projects.
|
|
|
|
|
|
|
|
LiteX is based on Migen.
|
2015-11-07 06:26:46 -05:00
|
|
|
|
|
|
|
[> License
|
|
|
|
-----------
|
2015-11-11 07:15:54 -05:00
|
|
|
LiteX is Copyright (c) 2012-2015 Enjoy-Digital under BSD Lisense.
|
2015-11-11 06:10:55 -05:00
|
|
|
Since it is based on MiSoC, please also refer to LICENSE file in soc directory
|
|
|
|
or git history to get correct copyrights.
|
2015-11-07 06:26:46 -05:00
|
|
|
|
|
|
|
[> Sub-packages
|
2015-11-11 06:10:55 -05:00
|
|
|
----------------
|
2015-11-07 06:26:46 -05:00
|
|
|
gen:
|
2015-11-11 06:10:55 -05:00
|
|
|
Provides specific or experimentatl modules to generate HDL that are not integrated
|
|
|
|
in Migen.
|
2015-11-07 06:26:46 -05:00
|
|
|
|
|
|
|
build:
|
|
|
|
Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
|
|
|
|
simulate HDL code or full SoCs.
|
|
|
|
|
|
|
|
soc:
|
|
|
|
Provides definitions/modules to build cores (bus, bank, flow), cores and tools
|
|
|
|
to build a SoC from such cores.
|
|
|
|
|
|
|
|
boards:
|
|
|
|
Provides platforms and targets for the supported boards.
|
|
|
|
|
2015-11-07 18:11:58 -05:00
|
|
|
[> Quick start guide
|
|
|
|
--------------------
|
|
|
|
0. If cloned from Git without the --recursive option, get the submodules:
|
|
|
|
git submodule update --init
|
|
|
|
|
2015-11-11 07:15:54 -05:00
|
|
|
1. Install Python 3.3+, Migen and FPGA vendor's development tools and JTAG tools.
|
|
|
|
Get Migen from: https://github.com/m-labs/migen
|
2015-11-07 18:11:58 -05:00
|
|
|
|
|
|
|
2. Compile and install binutils. Take the latest version from GNU.
|
|
|
|
mkdir build && cd build
|
|
|
|
../configure --target=lm32-elf
|
|
|
|
make
|
|
|
|
make install
|
|
|
|
|
|
|
|
3. (Optional, only if you want to use a lm32 CPU in you SoC)
|
|
|
|
Compile and install GCC. Take gcc-core and gcc-g++ from GNU
|
|
|
|
(version 4.5 or >=4.9).
|
|
|
|
rm -rf libstdc++-v3
|
|
|
|
mkdir build && cd build
|
|
|
|
../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
|
|
|
|
--disable-libssp
|
|
|
|
make
|
|
|
|
make install
|
|
|
|
|
|
|
|
4. Build the target of your board...:
|
|
|
|
Go to boards/targets and execute the target you want to build
|
|
|
|
|
|
|
|
5. ... and/or install Verilator and test LiteX on your computer:
|
|
|
|
Download and install Verilator: http://www.veripool.org/
|
|
|
|
Go to boards/targets
|
|
|
|
./sim.py
|
|
|
|
|
|
|
|
6. Run a terminal program on the board's serial port at 115200 8-N-1.
|
|
|
|
You should get the BIOS prompt.
|
|
|
|
|
2015-11-07 06:26:46 -05:00
|
|
|
[> Contact
|
|
|
|
E-mail: florent [AT] enjoy-digital.fr
|