25 lines
674 B
Python
25 lines
674 B
Python
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from mibuild.generic_platform import *
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from mibuild.xilinx_common import CRG_DS
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from mibuild.xilinx_vivado import XilinxVivadoPlatform
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_io = [
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("sys_clk", 0, Pins("X")),
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("sys_rst", 1, Pins("X")),
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("sata", 0,
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Subsignal("refclk_p", Pins("C8")),
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Subsignal("refclk_n", Pins("C7")),
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Subsignal("txp", Pins("D2")),
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Subsignal("txn", Pins("D1")),
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Subsignal("rxp", Pins("E4")),
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Subsignal("rxn", Pins("E3")),
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),
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]
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class Platform(XilinxVivadoPlatform):
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def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset"), **kwargs):
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XilinxVivadoPlatform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
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def do_finalize(self, *args, **kwargs):
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pass
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