Florent Kermarrec 473997df26 cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)		2015-03-02 16:52:17 +01:00
..
flash	flash/spi: make bitbang optional (enabled by default)	2015-03-01 17:15:22 +01:00
litesata	liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen	2015-03-01 16:48:41 +01:00
sdram	cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)	2015-03-02 16:52:17 +01:00
__init__.py	misoclib: better organization (create cores categories: cpu, mem, com, ...)	2015-02-28 09:40:44 +01:00