litex/targets/simple.py

28 lines
1004 B
Python
Raw Normal View History

2013-11-24 17:52:05 -05:00
from migen.fhdl.std import *
2013-11-25 09:08:53 -05:00
from misoclib import gpio, spiflash
2013-11-25 04:22:14 -05:00
from misoclib.gensoc import GenSoC, IntegratedBIOS
2013-11-24 17:52:05 -05:00
2013-11-25 04:22:14 -05:00
class SimpleSoC(GenSoC, IntegratedBIOS):
2013-11-24 17:52:05 -05:00
def __init__(self, platform):
GenSoC.__init__(self, platform,
clk_freq=32*1000000,
cpu_reset_address=0,
sram_size=4096)
2013-11-25 04:22:14 -05:00
IntegratedBIOS.__init__(self)
2013-11-24 17:52:05 -05:00
# We can't use reset_less as LM32 does require a reset signal
self.clock_domains.cd_sys = ClockDomain()
self.comb += self.cd_sys.clk.eq(platform.request("clk32"))
self.specials += Instance("FD", p_INIT=1, i_D=0, o_Q=self.cd_sys.rst, i_C=ClockSignal())
2013-11-25 06:16:20 -05:00
self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
2013-11-25 09:08:53 -05:00
# Map the SPI flash at 0xb0000000 for demo purposes. Later, we'll want to store the BIOS there.
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"),
cmd=0xefef, cmd_width=16, addr_width=24, dummy=4)
self.add_wb_slave(lambda a: a[26:29] == 3, self.spiflash.bus)
2013-11-24 17:52:05 -05:00
def get_default_subtarget(platform):
return SimpleSoC