36 lines
1.0 KiB
Python
36 lines
1.0 KiB
Python
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from migen.fhdl.std import *
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from migen.genlib.roundrobin import *
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from migen.genlib.record import Record
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from liteusb.ftdi.std import *
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class FtdiCrossbar(Module):
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def __init__(self, masters, slave=None):
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if slave is None:
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slave = FtdiPipe(user_layout)
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self.slave = slave
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# masters --> slave arbitration
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self.submodules.rr = RoundRobin(len(masters))
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cases = {}
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for i, m in enumerate(masters):
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sop = Signal()
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eop = Signal()
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ongoing = Signal()
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self.comb += [
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sop.eq(m.source.stb & m.source.sop),
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eop.eq(m.source.stb & m.source.eop & m.source.ack),
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]
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self.sync += ongoing.eq((sop | ongoing) & ~eop)
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self.comb += self.rr.request[i].eq(sop | ongoing)
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cases[i] = [Record.connect(masters[i].source, slave.source)]
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self.comb += Case(self.rr.grant, cases)
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# slave --> master demux
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cases = {}
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for i, m in enumerate(masters):
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cases[m.tag] = [Record.connect(slave.sink, masters[i].sink)]
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cases["default"] = [slave.sink.ack.eq(1)]
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self.comb += Case(slave.sink.dst, cases)
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