add ft2232h hdl code (will need rework)
This commit is contained in:
Florent Kermarrec
parent
1b0bc5ca44
commit
b59c777cab
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@ -0,0 +1,58 @@
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from migen.fhdl.std import *
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from migen.genlib.fsm import *
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from migen.actorlib.fifo import *
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from migen.flow.actor import EndpointDescription
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user_layout = EndpointDescription(
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[ ("dst", 8),
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("length", 4*8),
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("error", 1),
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("d", 8)
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],
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packetized=True
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)
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phy_layout = [
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("d", 8)
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]
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class FtdiPipe:
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def __init__(self, layout):
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self.sink = Sink(layout)
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self.source = Source(layout)
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class FtdiTimeout(Module):
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def __init__(self, clk_freq, length):
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cnt_max = int(clk_freq*length)
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width = bits_for(cnt_max)
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self.clear = Signal()
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self.done = Signal()
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cnt = Signal(width)
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self.sync += \
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If(self.clear,
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cnt.eq(0)
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).Elif(~self.done,
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cnt.eq(cnt+1)
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)
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self.comb += self.done.eq(cnt == cnt_max)
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#
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# TB
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#
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import random
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def randn(max_n):
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return random.randint(0, max_n-1)
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class RandRun:
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def __init__(self, level=0):
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self.run = True
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self.level = level
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def do_simulation(self, selfp):
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self.run = True
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n = randn(100)
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if n < self.level:
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self.run = False
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@ -0,0 +1,4 @@
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from liteusb.ftdi.uart import FtdiUART
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from liteusb.ftdi.dma import FtdiDMA
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from liteusb.ftdi.com import FtdiCom
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from liteusb.ftdi.crc import FtdiCRC32
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from migen.fhdl.std import *
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from migen.flow.actor import *
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from liteusb.ftdi.std import *
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from liteusb.ftdi.crossbar import FtdiCrossbar
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from liteusb.ftdi.packetizer import FtdiPacketizer
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from liteusb.ftdi.depacketizer import FtdiDepacketizer
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from liteusb.ftdi.phy import FtdiPHY
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class FtdiCom(Module):
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def __init__(self, pads, *ports):
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# crossbar
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self.submodules.crossbar = FtdiCrossbar(list(ports))
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# packetizer / depacketizer
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self.submodules.packetizer = FtdiPacketizer()
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self.submodules.depacketizer = FtdiDepacketizer()
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self.comb += [
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self.crossbar.slave.source.connect(self.packetizer.sink),
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self.depacketizer.source.connect(self.crossbar.slave.sink)
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]
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# phy
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self.submodules.phy = FtdiPHY(pads)
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self.comb += [
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self.packetizer.source.connect(self.phy.sink),
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self.phy.source.connect(self.depacketizer.sink)
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]
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@ -0,0 +1,298 @@
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from collections import OrderedDict
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from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.record import *
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from migen.genlib.misc import chooser, optree
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from migen.flow.actor import Sink, Source
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from migen.actorlib.fifo import SyncFIFO
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from liteusb.ftdi.std import *
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class CRCEngine(Module):
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"""Cyclic Redundancy Check Engine
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Compute next CRC value from last CRC value and data input using
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an optimized asynchronous LFSR.
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Parameters
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----------
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dat_width : int
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Width of the data bus.
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width : int
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Width of the CRC.
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polynom : int
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Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
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Attributes
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----------
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d : in
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Data input.
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last : in
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last CRC value.
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next :
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next CRC value.
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"""
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def __init__(self, dat_width, width, polynom):
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self.d = Signal(dat_width)
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self.last = Signal(width)
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self.next = Signal(width)
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###
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def _optimize_eq(l):
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"""
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Replace even numbers of XORs in the equation
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with an equivalent XOR
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"""
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d = OrderedDict()
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for e in l:
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if e in d:
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d[e] += 1
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else:
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d[e] = 1
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r = []
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for key, value in d.items():
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if value%2 != 0:
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r.append(key)
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return r
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# compute and optimize CRC's LFSR
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curval = [[("state", i)] for i in range(width)]
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for i in range(dat_width):
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feedback = curval.pop() + [("din", i)]
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for j in range(width-1):
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if (polynom & (1<<(j+1))):
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curval[j] += feedback
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curval[j] = _optimize_eq(curval[j])
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curval.insert(0, feedback)
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# implement logic
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for i in range(width):
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xors = []
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for t, n in curval[i]:
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if t == "state":
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xors += [self.last[n]]
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elif t == "din":
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xors += [self.d[n]]
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self.comb += self.next[i].eq(optree("^", xors))
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class CRC32(Module):
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"""IEEE 802.3 CRC
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Implement an IEEE 802.3 CRC generator/checker.
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Parameters
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----------
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dat_width : int
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Width of the data bus.
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Attributes
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----------
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d : in
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Data input.
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value : out
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CRC value (used for generator).
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error : out
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CRC error (used for checker).
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"""
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width = 32
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polynom = 0x04C11DB7
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init = 2**width-1
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check = 0xC704DD7B
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def __init__(self, dat_width):
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self.d = Signal(dat_width)
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self.value = Signal(self.width)
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self.error = Signal()
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###
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self.submodules.engine = CRCEngine(dat_width, self.width, self.polynom)
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reg = Signal(self.width, reset=self.init)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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self.engine.d.eq(self.d),
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self.engine.last.eq(reg),
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self.value.eq(~reg[::-1]),
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self.error.eq(self.engine.next != self.check)
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]
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class CRCInserter(Module):
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"""CRC Inserter
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Append a CRC at the end of each packet.
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Parameters
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----------
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layout : layout
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Layout of the dataflow.
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Attributes
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----------
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sink : in
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Packets input without CRC.
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source : out
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Packets output with CRC.
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"""
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def __init__(self, crc_class, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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self.busy = Signal()
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###
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dw = flen(sink.d)
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crc = crc_class(dw)
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fsm = FSM(reset_state="IDLE")
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self.submodules += crc, fsm
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fsm.act("IDLE",
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crc.reset.eq(1),
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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crc.ce.eq(sink.stb & source.ack),
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crc.d.eq(sink.d),
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Record.connect(sink, source),
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source.eop.eq(0),
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If(sink.stb & sink.eop & source.ack,
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NextState("INSERT"),
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)
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)
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ratio = crc.width//dw
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if ratio > 1:
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cnt = Signal(max=ratio, reset=ratio-1)
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cnt_done = Signal()
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fsm.act("INSERT",
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source.stb.eq(1),
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chooser(crc.value, cnt, source.d, reverse=True),
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If(cnt_done,
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source.eop.eq(1),
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If(source.ack, NextState("IDLE"))
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)
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)
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self.comb += cnt_done.eq(cnt == 0)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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cnt.eq(cnt.reset)
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).Elif(fsm.ongoing("INSERT") & ~cnt_done,
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cnt.eq(cnt - source.ack)
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)
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else:
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fsm.act("INSERT",
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source.stb.eq(1),
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source.eop.eq(1),
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source.d.eq(crc.value),
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If(source.ack, NextState("IDLE"))
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class CRC32Inserter(CRCInserter):
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def __init__(self, layout):
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CRCInserter.__init__(self, CRC32, layout)
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class CRCChecker(Module):
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"""CRC Checker
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Check CRC at the end of each packet.
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Parameters
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----------
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layout : layout
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Layout of the dataflow.
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Attributes
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----------
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sink : in
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Packets input with CRC.
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source : out
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Packets output without CRC and "error" set to 0
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on eop when CRC OK / set to 1 when CRC KO.
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"""
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def __init__(self, crc_class, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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self.busy = Signal()
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###
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dw = flen(sink.d)
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crc = crc_class(dw)
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self.submodules += crc
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ratio = crc.width//dw
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error = Signal()
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fifo = InsertReset(SyncFIFO(layout, ratio + 1))
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self.submodules += fifo
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fsm = FSM(reset_state="RESET")
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self.submodules += fsm
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fifo_in = Signal()
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fifo_out = Signal()
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fifo_full = Signal()
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self.comb += [
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fifo_full.eq(fifo.fifo.level == ratio),
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fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
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fifo_out.eq(source.stb & source.ack),
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Record.connect(sink, fifo.sink),
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fifo.sink.stb.eq(fifo_in),
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self.sink.ack.eq(fifo_in),
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source.stb.eq(sink.stb & fifo_full),
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source.sop.eq(fifo.source.sop),
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source.eop.eq(sink.eop),
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fifo.source.ack.eq(fifo_out),
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source.payload.eq(fifo.source.payload),
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source.error.eq(sink.error | crc.error),
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]
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fsm.act("RESET",
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crc.reset.eq(1),
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fifo.reset.eq(1),
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NextState("IDLE"),
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)
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fsm.act("IDLE",
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crc.d.eq(sink.d),
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If(sink.stb & sink.sop & sink.ack,
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crc.ce.eq(1),
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NextState("COPY")
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)
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)
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fsm.act("COPY",
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crc.d.eq(sink.d),
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If(sink.stb & sink.ack,
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crc.ce.eq(1),
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If(sink.eop,
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NextState("RESET")
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)
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)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class CRC32Checker(CRCChecker):
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def __init__(self, layout):
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CRCChecker.__init__(self, CRC32, layout)
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class FtdiCRC32(Module):
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def __init__(self, tag):
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self.tag = tag
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self.submodules.inserter = CRC32Inserter(user_layout)
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self.submodules.checker = CRC32Checker(user_layout)
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self.dma_sink = self.inserter.sink
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self.dma_source = self.checker.source
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self.sink = self.checker.sink
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self.source = self.inserter.source
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@ -0,0 +1,153 @@
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from migen.fhdl.std import *
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from migen.actorlib.structuring import *
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from migen.genlib.fsm import FSM, NextState
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from liteusb.ftdi.std import *
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class FtdiDepacketizer(Module):
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def __init__(self, timeout=10):
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self.sink = sink = Sink(phy_layout)
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self.source = source = Source(user_layout)
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# Packet description
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# - preamble : 4 bytes
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# - dst : 1 byte
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# - length : 4 bytes
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# - payload
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preamble = Array(Signal(8) for i in range(4))
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header = [
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# dst
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source.dst,
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# length
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source.length[24:32],
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source.length[16:24],
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source.length[8:16],
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source.length[0:8],
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]
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header_pack = InsertReset(Pack(phy_layout, len(header)))
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self.submodules += header_pack
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for i, byte in enumerate(header):
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chunk = getattr(header_pack.source.payload, "chunk" + str(i))
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self.comb += byte.eq(chunk.d)
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fsm = FSM()
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self.submodules += fsm
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self.comb += preamble[0].eq(sink.d)
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for i in range(1, 4):
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self.sync += If(sink.stb & sink.ack,
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preamble[i].eq(preamble[i-1])
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)
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fsm.act("WAIT_SOP",
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If( (preamble[3] == 0x5A) &
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(preamble[2] == 0xA5) &
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(preamble[1] == 0x5A) &
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(preamble[0] == 0xA5) &
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sink.stb,
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NextState("RECEIVE_HEADER")
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),
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sink.ack.eq(1),
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header_pack.source.ack.eq(1),
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)
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self.submodules.timeout = FtdiTimeout(60000000, timeout)
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self.comb += self.timeout.clear.eq(fsm.ongoing("WAIT_SOP"))
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fsm.act("RECEIVE_HEADER",
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header_pack.sink.stb.eq(sink.stb),
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header_pack.sink.payload.eq(sink.payload),
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If(self.timeout.done, NextState("WAIT_SOP"))
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.Elif(header_pack.source.stb, NextState("RECEIVE_PAYLOAD"))
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.Else(sink.ack.eq(1))
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)
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self.comb += header_pack.reset.eq(self.timeout.done)
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sop = Signal()
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eop = Signal()
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cnt = Signal(32)
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fsm.act("RECEIVE_PAYLOAD",
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source.stb.eq(sink.stb),
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source.sop.eq(sop),
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source.eop.eq(eop),
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source.d.eq(sink.d),
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sink.ack.eq(source.ack),
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If((eop & sink.stb & source.ack) | self.timeout.done, NextState("WAIT_SOP"))
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)
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self.sync += \
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If(fsm.ongoing("WAIT_SOP"),
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cnt.eq(0)
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).Elif(source.stb & source.ack,
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cnt.eq(cnt + 1)
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)
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self.comb += sop.eq(cnt == 0)
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self.comb += eop.eq(cnt == source.length - 1)
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#
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# TB
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#
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src_data = [
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0x5A, 0xA5, 0x5A, 0xA5, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x02, 0x03,
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0x5A, 0xA5, 0x5A, 0xA5, 0x12, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
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]*4
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class DepacketizerSourceModel(Module, Source, RandRun):
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def __init__(self, data):
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Source.__init__(self, phy_layout)
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RandRun.__init__(self, 50)
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self.data = data
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self._stb = 0
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self._cnt = 0
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def do_simulation(self, selfp):
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RandRun.do_simulation(self, selfp)
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if self.run and not self._stb:
|
||||
self._stb = 1
|
||||
|
||||
if selfp.stb and selfp.ack:
|
||||
self._cnt +=1
|
||||
|
||||
selfp.stb = self._stb
|
||||
selfp.d = self.data[self._cnt]
|
||||
|
||||
if self._cnt == len(self.data)-1:
|
||||
raise StopSimulation
|
||||
|
||||
|
||||
class DepacketizerSinkModel(Module, Sink, RandRun):
|
||||
def __init__(self):
|
||||
Sink.__init__(self, user_layout, True)
|
||||
RandRun.__init__(self, 50)
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
RandRun.do_simulation(self, selfp)
|
||||
if self.run:
|
||||
selfp.ack = 1
|
||||
else:
|
||||
selfp.ack = 0
|
||||
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.source = DepacketizerSourceModel(src_data)
|
||||
self.submodules.dut = FtdiDepacketizer()
|
||||
self.submodules.sink = DepacketizerSinkModel()
|
||||
|
||||
self.comb += [
|
||||
self.source.connect(self.dut.sink),
|
||||
self.dut.source.connect(self.sink),
|
||||
]
|
||||
|
||||
def main():
|
||||
from migen.sim.generic import run_simulation
|
||||
run_simulation(TB(), ncycles=400, vcd_name="tb_depacketizer.vcd")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.actorlib.structuring import *
|
||||
from migen.genlib.fsm import FSM, NextState
|
||||
|
||||
from liteusb.ftdi.std import *
|
||||
|
||||
class FtdiPacketizer(Module):
|
||||
def __init__(self):
|
||||
self.sink = sink = Sink(user_layout)
|
||||
self.source = source = Source(phy_layout)
|
||||
|
||||
# Packet description
|
||||
# - preamble : 4 bytes
|
||||
# - dst : 1 byte
|
||||
# - length : 4 bytes
|
||||
# - payload
|
||||
header = [
|
||||
# preamble
|
||||
0x5A,
|
||||
0xA5,
|
||||
0x5A,
|
||||
0xA5,
|
||||
# dst
|
||||
sink.dst,
|
||||
# length
|
||||
sink.length[24:32],
|
||||
sink.length[16:24],
|
||||
sink.length[8:16],
|
||||
sink.length[0:8],
|
||||
]
|
||||
|
||||
header_unpack = Unpack(len(header), phy_layout)
|
||||
self.submodules += header_unpack
|
||||
|
||||
for i, byte in enumerate(header):
|
||||
chunk = getattr(header_unpack.sink.payload, "chunk" + str(i))
|
||||
self.comb += chunk.d.eq(byte)
|
||||
|
||||
fsm = FSM()
|
||||
self.submodules += fsm
|
||||
|
||||
fsm.act("WAIT_SOP",
|
||||
If(sink.stb & sink.sop, NextState("SEND_HEADER"))
|
||||
)
|
||||
|
||||
fsm.act("SEND_HEADER",
|
||||
header_unpack.sink.stb.eq(1),
|
||||
source.stb.eq(1),
|
||||
source.d.eq(header_unpack.source.d),
|
||||
header_unpack.source.ack.eq(source.ack),
|
||||
If(header_unpack.sink.ack, NextState("SEND_DATA"))
|
||||
)
|
||||
|
||||
fsm.act("SEND_DATA",
|
||||
source.stb.eq(sink.stb),
|
||||
source.d.eq(sink.d),
|
||||
sink.ack.eq(source.ack),
|
||||
If(source.ack & sink.eop, NextState("WAIT_SOP"))
|
||||
)
|
||||
|
||||
#
|
||||
# TB
|
||||
#
|
||||
src_data = [
|
||||
(0x01, 4,
|
||||
[0x0, 0x1, 0x2, 0x3]
|
||||
),
|
||||
(0x16, 8,
|
||||
[0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7]
|
||||
),
|
||||
(0x22, 16,
|
||||
[0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF]
|
||||
),
|
||||
]
|
||||
|
||||
class PacketizerSourceModel(Module, Source, RandRun):
|
||||
def __init__(self, data):
|
||||
Source.__init__(self, user_layout, True)
|
||||
RandRun.__init__(self, 25)
|
||||
self.data = data
|
||||
|
||||
self._stb = 0
|
||||
self._sop = 0
|
||||
self._eop = 0
|
||||
self._frame_cnt = 0
|
||||
self._payload_cnt = 0
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
RandRun.do_simulation(self, selfp)
|
||||
dst, length, payload = self.data[self._frame_cnt]
|
||||
|
||||
if selfp.stb and selfp.ack:
|
||||
if self._payload_cnt == length-1:
|
||||
self._frame_cnt += 1
|
||||
self._payload_cnt = 0
|
||||
else:
|
||||
self._payload_cnt += 1
|
||||
if self.run:
|
||||
self._stb = 1
|
||||
else:
|
||||
self._stb = 0
|
||||
|
||||
if self.run and not self._stb:
|
||||
self._stb = 1
|
||||
|
||||
self._sop = int((self._payload_cnt == 0))
|
||||
self._eop = int((self._payload_cnt == length-1))
|
||||
|
||||
selfp.stb = self._stb
|
||||
selfp.sop = self._sop & self._stb
|
||||
selfp.eop = self._eop & self._stb
|
||||
selfp.dst = dst
|
||||
selfp.length = length
|
||||
selfp.d = payload[self._payload_cnt]
|
||||
|
||||
if self._frame_cnt == len(self.data):
|
||||
raise StopSimulation
|
||||
|
||||
class PacketizerSinkModel(Module, Sink, RandRun):
|
||||
def __init__(self):
|
||||
Sink.__init__(self, phy_layout)
|
||||
RandRun.__init__(self, 25)
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
RandRun.do_simulation(self, selfp)
|
||||
if self.run:
|
||||
selfp.ack = 1
|
||||
else:
|
||||
selfp.ack = 0
|
||||
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.source = PacketizerSourceModel(src_data)
|
||||
self.submodules.dut = FtdiPacketizer()
|
||||
self.submodules.sink = PacketizerSinkModel()
|
||||
|
||||
self.comb +=[
|
||||
self.source.connect(self.dut.sink),
|
||||
self.dut.source.connect(self.sink),
|
||||
]
|
||||
|
||||
def main():
|
||||
from migen.sim.generic import run_simulation
|
||||
run_simulation(TB(), ncycles=400, vcd_name="tb_packetizer.vcd")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.genlib.roundrobin import *
|
||||
from migen.genlib.record import Record
|
||||
|
||||
from liteusb.ftdi.std import *
|
||||
|
||||
class FtdiCrossbar(Module):
|
||||
def __init__(self, masters, slave=None):
|
||||
if slave is None:
|
||||
slave = FtdiPipe(user_layout)
|
||||
self.slave = slave
|
||||
|
||||
# masters --> slave arbitration
|
||||
self.submodules.rr = RoundRobin(len(masters))
|
||||
cases = {}
|
||||
for i, m in enumerate(masters):
|
||||
sop = Signal()
|
||||
eop = Signal()
|
||||
ongoing = Signal()
|
||||
self.comb += [
|
||||
sop.eq(m.source.stb & m.source.sop),
|
||||
eop.eq(m.source.stb & m.source.eop & m.source.ack),
|
||||
]
|
||||
self.sync += ongoing.eq((sop | ongoing) & ~eop)
|
||||
self.comb += self.rr.request[i].eq(sop | ongoing)
|
||||
|
||||
cases[i] = [Record.connect(masters[i].source, slave.source)]
|
||||
self.comb += Case(self.rr.grant, cases)
|
||||
|
||||
# slave --> master demux
|
||||
cases = {}
|
||||
for i, m in enumerate(masters):
|
||||
cases[m.tag] = [Record.connect(slave.sink, masters[i].sink)]
|
||||
cases["default"] = [slave.sink.ack.eq(1)]
|
||||
self.comb += Case(slave.sink.dst, cases)
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.flow.actor import *
|
||||
from migen.flow.network import *
|
||||
from migen.actorlib import dma_lasmi, structuring, spi
|
||||
from migen.bank.description import *
|
||||
from migen.bank.eventmanager import *
|
||||
from migen.genlib.record import Record
|
||||
|
||||
from liteusb.ftdi.std import *
|
||||
|
||||
class FtdiDMAWriter(Module, AutoCSR):
|
||||
def __init__(self, lasmim):
|
||||
self.sink = sink = Sink(user_layout)
|
||||
|
||||
# Pack data
|
||||
pack_factor = lasmim.dw//8
|
||||
pack = structuring.Pack(phy_layout, pack_factor, reverse=True)
|
||||
cast = structuring.Cast(pack.source.payload.layout, lasmim.dw)
|
||||
|
||||
# DMA
|
||||
writer = dma_lasmi.Writer(lasmim)
|
||||
self._reset = CSR()
|
||||
self.dma = InsertReset(spi.DMAWriteController(writer, mode=spi.MODE_SINGLE_SHOT))
|
||||
self.comb += self.dma.reset.eq(self._reset.r & self._reset.re)
|
||||
|
||||
# Remove sop/eop/length/dst fields from payload
|
||||
self.comb += [
|
||||
pack.sink.stb.eq(sink.stb),
|
||||
pack.sink.payload.eq(sink.payload),
|
||||
sink.ack.eq(pack.sink.ack)
|
||||
]
|
||||
|
||||
# Graph
|
||||
g = DataFlowGraph()
|
||||
g.add_pipeline(pack, cast, self.dma)
|
||||
self.submodules += CompositeActor(g)
|
||||
|
||||
# IRQ
|
||||
self.submodules.ev = EventManager()
|
||||
self.ev.done = EventSourcePulse()
|
||||
self.ev.finalize()
|
||||
self.comb += self.ev.done.trigger.eq(sink.stb & sink.eop)
|
||||
|
||||
# CRC
|
||||
self._crc_failed = CSRStatus()
|
||||
self.sync += \
|
||||
If(sink.stb & sink.eop,
|
||||
self._crc_failed.status.eq(sink.error)
|
||||
)
|
||||
|
||||
class FtdiDMAReader(Module, AutoCSR):
|
||||
def __init__(self, lasmim, tag):
|
||||
self.source = source = Source(user_layout)
|
||||
|
||||
reader = dma_lasmi.Reader(lasmim)
|
||||
self.dma = spi.DMAReadController(reader, mode=spi.MODE_SINGLE_SHOT)
|
||||
|
||||
pack_factor = lasmim.dw//8
|
||||
packed_dat = structuring.pack_layout(8, pack_factor)
|
||||
cast = structuring.Cast(lasmim.dw, packed_dat)
|
||||
unpack = structuring.Unpack(pack_factor, phy_layout, reverse=True)
|
||||
|
||||
# Graph
|
||||
cnt = Signal(32)
|
||||
self.sync += \
|
||||
If(self.dma.generator._r_shoot.re,
|
||||
cnt.eq(0)
|
||||
).Elif(source.stb & source.ack,
|
||||
cnt.eq(cnt + 1)
|
||||
)
|
||||
g = DataFlowGraph()
|
||||
g.add_pipeline(self.dma, cast, unpack)
|
||||
self.submodules += CompositeActor(g)
|
||||
self.comb += [
|
||||
source.stb.eq(unpack.source.stb),
|
||||
source.sop.eq(cnt == 0),
|
||||
source.eop.eq(cnt == (self.dma.length*pack_factor-1)),
|
||||
source.length.eq(self.dma.length*pack_factor+4),
|
||||
source.d.eq(unpack.source.d),
|
||||
source.dst.eq(tag),
|
||||
unpack.source.ack.eq(source.ack)
|
||||
]
|
||||
|
||||
# IRQ
|
||||
self.submodules.ev = EventManager()
|
||||
self.ev.done = EventSourcePulse()
|
||||
self.ev.finalize()
|
||||
self.comb += self.ev.done.trigger.eq(source.stb & source.eop)
|
||||
|
||||
class FtdiDMA(Module, AutoCSR):
|
||||
def __init__(self, lasmim_ftdi_dma_wr, lasmim_ftdi_dma_rd, tag):
|
||||
self.tag = tag
|
||||
|
||||
self.submodules.writer = FtdiDMAWriter(lasmim_ftdi_dma_wr)
|
||||
self.submodules.reader = FtdiDMAReader(lasmim_ftdi_dma_rd, self.tag)
|
||||
self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)
|
||||
|
||||
self.sink = self.writer.sink
|
||||
self.source = self.reader.source
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.bank.description import *
|
||||
from migen.bank.eventmanager import *
|
||||
from migen.genlib.fifo import SyncFIFOBuffered
|
||||
|
||||
from liteusb.ftdi.std import *
|
||||
|
||||
class FtdiUART(Module, AutoCSR):
|
||||
def __init__(self, tag, fifo_depth=64):
|
||||
self.tag = tag
|
||||
|
||||
self._rxtx = CSR(8)
|
||||
|
||||
self.submodules.ev = EventManager()
|
||||
self.ev.tx = EventSourcePulse()
|
||||
self.ev.rx = EventSourceLevel()
|
||||
self.ev.finalize()
|
||||
|
||||
self.source = source = Source(user_layout)
|
||||
self.sink = sink = Sink(user_layout)
|
||||
|
||||
###
|
||||
|
||||
# TX
|
||||
tx_start = self._rxtx.re
|
||||
tx_done = self.ev.tx.trigger
|
||||
|
||||
self.sync += \
|
||||
If(tx_start,
|
||||
source.stb.eq(1),
|
||||
source.d.eq(self._rxtx.r),
|
||||
).Elif(tx_done,
|
||||
source.stb.eq(0)
|
||||
)
|
||||
|
||||
self.comb += [
|
||||
source.sop.eq(1),
|
||||
source.eop.eq(1),
|
||||
source.length.eq(1),
|
||||
source.dst.eq(self.tag),
|
||||
tx_done.eq(source.stb & source.ack),
|
||||
]
|
||||
|
||||
# RX
|
||||
rx_available = self.ev.rx.trigger
|
||||
|
||||
rx_fifo = SyncFIFOBuffered(8, fifo_depth)
|
||||
self.submodules += rx_fifo
|
||||
self.comb += [
|
||||
rx_fifo.we.eq(sink.stb),
|
||||
sink.ack.eq(sink.stb & rx_fifo.writable),
|
||||
rx_fifo.din.eq(sink.d),
|
||||
|
||||
rx_available.eq(rx_fifo.readable),
|
||||
rx_fifo.re.eq(self.ev.rx.clear),
|
||||
self._rxtx.w.eq(rx_fifo.dout)
|
||||
]
|
||||
|
|
@ -0,0 +1,307 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.flow.actor import *
|
||||
from migen.actorlib.fifo import AsyncFIFO
|
||||
from migen.fhdl.specials import *
|
||||
|
||||
from liteusb.ftdi.std import *
|
||||
|
||||
class FtdiPHY(Module):
|
||||
def __init__(self, pads, fifo_depth=32, read_time=16, write_time=16):
|
||||
dw = flen(pads.data)
|
||||
|
||||
#
|
||||
# Read / Write Fifos
|
||||
#
|
||||
|
||||
# Read Fifo (Ftdi --> SoC)
|
||||
read_fifo = RenameClockDomains(AsyncFIFO(phy_layout, fifo_depth),
|
||||
{"write":"ftdi", "read":"sys"})
|
||||
read_buffer = RenameClockDomains(SyncFIFO(phy_layout, 4),
|
||||
{"sys":"ftdi"})
|
||||
self.comb += read_buffer.source.connect(read_fifo.sink)
|
||||
|
||||
# Write Fifo (SoC --> Ftdi)
|
||||
write_fifo = RenameClockDomains(AsyncFIFO(phy_layout, fifo_depth),
|
||||
{"write":"sys", "read":"ftdi"})
|
||||
|
||||
self.submodules += read_fifo, read_buffer, write_fifo
|
||||
|
||||
#
|
||||
# Sink / Source interfaces
|
||||
#
|
||||
self.sink = write_fifo.sink
|
||||
self.source = read_fifo.source
|
||||
|
||||
#
|
||||
# Read / Write Arbitration
|
||||
#
|
||||
wants_write = Signal()
|
||||
wants_read = Signal()
|
||||
|
||||
txe_n = Signal()
|
||||
rxf_n = Signal()
|
||||
|
||||
self.comb += [
|
||||
txe_n.eq(pads.txe_n),
|
||||
rxf_n.eq(pads.rxf_n),
|
||||
wants_write.eq(~txe_n & write_fifo.source.stb),
|
||||
wants_read.eq(~rxf_n & read_fifo.sink.ack),
|
||||
]
|
||||
|
||||
def anti_starvation(timeout):
|
||||
en = Signal()
|
||||
max_time = Signal()
|
||||
if timeout:
|
||||
t = timeout - 1
|
||||
time = Signal(max=t+1)
|
||||
self.comb += max_time.eq(time == 0)
|
||||
self.sync += If(~en,
|
||||
time.eq(t)
|
||||
).Elif(~max_time,
|
||||
time.eq(time - 1)
|
||||
)
|
||||
else:
|
||||
self.comb += max_time.eq(0)
|
||||
return en, max_time
|
||||
|
||||
read_time_en, max_read_time = anti_starvation(read_time)
|
||||
write_time_en, max_write_time = anti_starvation(write_time)
|
||||
|
||||
data_w_accepted = Signal(reset=1)
|
||||
|
||||
fsm = FSM()
|
||||
self.submodules += RenameClockDomains(fsm, {"sys": "ftdi"})
|
||||
|
||||
fsm.act("READ",
|
||||
read_time_en.eq(1),
|
||||
If(wants_write,
|
||||
If(~wants_read | max_read_time, NextState("RTW"))
|
||||
)
|
||||
)
|
||||
fsm.act("RTW",
|
||||
NextState("WRITE")
|
||||
)
|
||||
fsm.act("WRITE",
|
||||
write_time_en.eq(1),
|
||||
If(wants_read,
|
||||
If(~wants_write | max_write_time, NextState("WTR"))
|
||||
),
|
||||
write_fifo.source.ack.eq(wants_write & data_w_accepted)
|
||||
)
|
||||
fsm.act("WTR",
|
||||
NextState("READ")
|
||||
)
|
||||
|
||||
#
|
||||
# Read / Write Actions
|
||||
#
|
||||
|
||||
data_w = Signal(dw)
|
||||
data_r = Signal(dw)
|
||||
data_oe = Signal()
|
||||
|
||||
pads.oe_n.reset = 1
|
||||
pads.rd_n.reset = 1
|
||||
pads.wr_n.reset = 1
|
||||
|
||||
self.sync.ftdi += [
|
||||
If(fsm.ongoing("READ"),
|
||||
data_oe.eq(0),
|
||||
|
||||
pads.oe_n.eq(0),
|
||||
pads.rd_n.eq(~wants_read),
|
||||
pads.wr_n.eq(1)
|
||||
|
||||
).Elif(fsm.ongoing("WRITE"),
|
||||
data_oe.eq(1),
|
||||
|
||||
pads.oe_n.eq(1),
|
||||
pads.rd_n.eq(1),
|
||||
pads.wr_n.eq(~wants_write),
|
||||
|
||||
data_w_accepted.eq(~txe_n)
|
||||
|
||||
).Else(
|
||||
data_oe.eq(1),
|
||||
|
||||
pads.oe_n.eq(~fsm.ongoing("WTR")),
|
||||
pads.rd_n.eq(1),
|
||||
pads.wr_n.eq(1)
|
||||
),
|
||||
read_buffer.sink.stb.eq(~pads.rd_n & ~rxf_n),
|
||||
read_buffer.sink.d.eq(data_r),
|
||||
If(~txe_n & data_w_accepted,
|
||||
data_w.eq(write_fifo.source.d)
|
||||
)
|
||||
]
|
||||
|
||||
#
|
||||
# Databus Tristate
|
||||
#
|
||||
self.specials += Tristate(pads.data, data_w, data_oe, data_r)
|
||||
|
||||
self.debug = Signal(8)
|
||||
self.comb += self.debug.eq(data_r)
|
||||
|
||||
|
||||
#
|
||||
# TB
|
||||
#
|
||||
class FtdiModel(Module, RandRun):
|
||||
def __init__(self, rd_data):
|
||||
RandRun.__init__(self, 50)
|
||||
self.rd_data = [0] + rd_data
|
||||
self.rd_idx = 0
|
||||
|
||||
# pads
|
||||
self.data = Signal(8)
|
||||
self.rxf_n = Signal(reset=1)
|
||||
self.txe_n = Signal(reset=1)
|
||||
self.rd_n = Signal(reset=1)
|
||||
self.wr_n = Signal(reset=1)
|
||||
self.oe_n = Signal(reset=1)
|
||||
self.siwua = Signal()
|
||||
self.pwren_n = Signal(reset=1)
|
||||
|
||||
self.init = True
|
||||
self.wr_data = []
|
||||
self.wait_wr_n = False
|
||||
self.rd_done = 0
|
||||
|
||||
def wr_sim(self, selfp):
|
||||
if not selfp.wr_n and not selfp.txe_n:
|
||||
self.wr_data.append(selfp.data)
|
||||
self.wait_wr_n = False
|
||||
|
||||
if not self.wait_wr_n:
|
||||
if self.run:
|
||||
selfp.txe_n = 1
|
||||
else:
|
||||
if selfp.txe_n:
|
||||
self.wait_wr_n = True
|
||||
selfp.txe_n = 0
|
||||
|
||||
def rd_sim(self, selfp):
|
||||
rxf_n = selfp.rxf_n
|
||||
if self.run:
|
||||
if self.rd_idx < len(self.rd_data)-1:
|
||||
self.rd_done = selfp.rxf_n
|
||||
selfp.rxf_n = 0
|
||||
else:
|
||||
selfp.rxf_n = self.rd_done
|
||||
else:
|
||||
selfp.rxf_n = self.rd_done
|
||||
|
||||
if not selfp.rd_n and not selfp.oe_n:
|
||||
if self.rd_idx < len(self.rd_data)-1:
|
||||
self.rd_idx += not rxf_n
|
||||
selfp.data = self.rd_data[self.rd_idx]
|
||||
self.rd_done = 1
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
RandRun.do_simulation(self, selfp)
|
||||
if self.init:
|
||||
selfp.rxf_n = 0
|
||||
self.wr_data = []
|
||||
self.init = False
|
||||
self.wr_sim(selfp)
|
||||
self.rd_sim(selfp)
|
||||
|
||||
class UserModel(Module, RandRun):
|
||||
def __init__(self, wr_data):
|
||||
RandRun.__init__(self, 50)
|
||||
self.wr_data = wr_data
|
||||
self.wr_data_idx = 0
|
||||
|
||||
self.sink = Sink(phy_layout)
|
||||
self.source = Source(phy_layout)
|
||||
|
||||
self.rd_data = []
|
||||
|
||||
def wr_sim(self, selfp):
|
||||
auth = True
|
||||
if selfp.source.stb and not selfp.source.ack:
|
||||
auth = False
|
||||
if auth:
|
||||
if self.wr_data_idx < len(self.wr_data):
|
||||
if self.run:
|
||||
selfp.source.d = self.wr_data[self.wr_data_idx]
|
||||
selfp.source.stb = 1
|
||||
self.wr_data_idx += 1
|
||||
else:
|
||||
selfp.source.stb = 0
|
||||
else:
|
||||
self.source.stb = 0
|
||||
|
||||
def rd_sim(self, selfp):
|
||||
if self.run:
|
||||
selfp.sink.ack = 1
|
||||
else:
|
||||
selfp.sink.ack = 0
|
||||
if selfp.sink.stb & selfp.sink.ack:
|
||||
self.rd_data.append(selfp.sink.d)
|
||||
|
||||
def do_simulation(self, selfp):
|
||||
RandRun.do_simulation(self, selfp)
|
||||
self.wr_sim(selfp)
|
||||
self.rd_sim(selfp)
|
||||
|
||||
|
||||
LENGTH = 512
|
||||
model_rd_data = [i%256 for i in range(LENGTH)][::-1]
|
||||
user_wr_data = [i%256 for i in range(LENGTH)]
|
||||
|
||||
class TB(Module):
|
||||
def __init__(self):
|
||||
self.submodules.model = FtdiModel(model_rd_data)
|
||||
self.submodules.phy = FtdiPHY(self.model)
|
||||
|
||||
self.submodules.user = UserModel(user_wr_data)
|
||||
|
||||
self.comb += [
|
||||
self.user.source.connect(self.phy.sink),
|
||||
self.phy.source.connect(self.user.sink)
|
||||
]
|
||||
|
||||
# Use sys_clk as ftdi_clk in simulation
|
||||
self.comb += [
|
||||
ClockSignal("ftdi").eq(ClockSignal()),
|
||||
ResetSignal("ftdi").eq(ResetSignal())
|
||||
]
|
||||
|
||||
def print_results(s, l1, l2):
|
||||
def comp(l1, l2):
|
||||
r = True
|
||||
try:
|
||||
for i, val in enumerate(l1):
|
||||
if val != l2[i]:
|
||||
print(s + " : val : %02X, exp : %02X" %(val, l2[i]))
|
||||
r = False
|
||||
except:
|
||||
return r
|
||||
return r
|
||||
|
||||
c = comp(l1, l2)
|
||||
r = s + " "
|
||||
if c:
|
||||
r += "[OK]"
|
||||
else:
|
||||
r += "[KO]"
|
||||
print(r)
|
||||
|
||||
def main():
|
||||
from migen.sim.generic import run_simulation
|
||||
tb = TB()
|
||||
run_simulation(tb, ncycles=8000, vcd_name="tb_phy.vcd")
|
||||
|
||||
###
|
||||
#print(tb.user.rd_data)
|
||||
#print(tb.model.wr_data)
|
||||
#print(len(tb.user.rd_data))
|
||||
#print(len(tb.model.wr_data))
|
||||
|
||||
print_results("FtdiModel --> UserModel", model_rd_data, tb.user.rd_data)
|
||||
print_results("UserModel --> FtdiModel", user_wr_data, tb.model.wr_data)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
Loading…
Reference in New Issue