litex/misoclib/com/liteusb/test/Makefile

MSCDIR = ../../
PYTHON = python3

CMD = PYTHONPATH=$(MSCDIR) $(PYTHON)

ft245_sync_tb:
	$(CMD) ft245_sync_tb.py

ft245_async_tb:
	$(CMD) ft245_async_tb.py

core_tb:
	$(CMD) core_tb.py
liteusb: begin refactoring and simplification (wip) 2015-04-27 09:19:54 -04:00			`MSCDIR = ../../`
			`PYTHON = python3`

			`CMD = PYTHONPATH=$(MSCDIR) $(PYTHON)`

liteusb: continue refactoring (virtual UART and DMA working on minispartan6) - rename ft2232h phy to ft245. - make crc optional - fix depacketizer - refactor uart (it's now only a wrapper around standard UART) - fix and update dma 2015-05-01 10:11:15 -04:00			`ft245_sync_tb:`
			`$(CMD) ft245_sync_tb.py`
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests 2015-04-28 13:00:13 -04:00
liteusb: continue refactoring (virtual UART and DMA working on minispartan6) - rename ft2232h phy to ft245. - make crc optional - fix depacketizer - refactor uart (it's now only a wrapper around standard UART) - fix and update dma 2015-05-01 10:11:15 -04:00			`ft245_async_tb:`
			`$(CMD) ft245_async_tb.py`
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests 2015-04-28 13:00:13 -04:00
			`core_tb:`
			`$(CMD) core_tb.py`