litex/migen/bank/csrgen.py

100 lines
2.8 KiB
Python
Raw Normal View History

from migen.util.misc import xdir
from migen.fhdl.std import *
2012-08-26 15:19:34 -04:00
from migen.bus import csr
2011-12-16 10:02:55 -05:00
from migen.bank.description import *
2011-12-05 11:43:56 -05:00
def get_offset(description, name, csr_data_width=8):
offset = 0
for c in description:
if c.name == name:
return offset
offset += (c.size + csr_data_width - 1)//csr_data_width
raise KeyError("CSR not found: "+name)
2013-03-30 12:28:41 -04:00
class Bank(Module):
def __init__(self, description, address=0, bus=None):
if bus is None:
bus = csr.Interface()
2012-12-06 11:15:34 -05:00
self.bus = bus
2014-10-17 05:08:37 -04:00
2013-03-30 12:28:41 -04:00
###
if not description:
return
2014-10-17 05:08:37 -04:00
2013-03-30 12:28:41 -04:00
# Turn description into simple CSRs and claim ownership of compound CSR modules
simple_csrs = []
for c in description:
if isinstance(c, CSR):
simple_csrs.append(c)
else:
2013-07-28 10:33:36 -04:00
c.finalize(flen(self.bus.dat_w))
2013-03-30 12:28:41 -04:00
simple_csrs += c.get_simple_csrs()
self.submodules += c
nbits = bits_for(len(simple_csrs)-1)
# Decode selection
sel = Signal()
self.comb += sel.eq(self.bus.adr[9:] == address)
2014-10-17 05:08:37 -04:00
2011-12-05 11:43:56 -05:00
# Bus writes
2013-03-30 12:28:41 -04:00
for i, c in enumerate(simple_csrs):
self.comb += [
c.r.eq(self.bus.dat_w[:c.size]),
c.re.eq(sel & \
2012-12-06 11:15:34 -05:00
self.bus.we & \
2013-03-30 12:28:41 -04:00
(self.bus.adr[:nbits] == i))
]
2014-10-17 05:08:37 -04:00
2011-12-05 11:43:56 -05:00
# Bus reads
2013-03-30 12:28:41 -04:00
brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(simple_csrs))
self.sync += [
self.bus.dat_r.eq(0),
If(sel, Case(self.bus.adr[:nbits], brcases))
]
2013-03-09 18:45:16 -05:00
# address_map(name, memory) returns the CSR offset at which to map
# the CSR object (register bank or memory).
# If memory=None, the object is the register bank of object source.name.
# Otherwise, it is a memory object belonging to source.name.
# address_map is called exactly once for each object at each call to
# scan(), so it can have side effects.
2013-03-30 12:28:41 -04:00
class BankArray(Module):
2013-07-28 10:33:36 -04:00
def __init__(self, source, address_map, *ifargs, **ifkwargs):
2013-03-09 18:45:16 -05:00
self.source = source
self.address_map = address_map
2013-07-28 10:33:36 -04:00
self.scan(ifargs, ifkwargs)
2013-03-09 18:45:16 -05:00
2013-07-28 10:33:36 -04:00
def scan(self, ifargs, ifkwargs):
2013-03-09 18:45:16 -05:00
self.banks = []
self.srams = []
for name, obj in xdir(self.source, True):
2013-03-30 12:28:41 -04:00
if hasattr(obj, "get_csrs"):
csrs = obj.get_csrs()
2013-03-09 18:45:16 -05:00
else:
2013-03-30 12:28:41 -04:00
csrs = []
2013-03-09 18:45:16 -05:00
if hasattr(obj, "get_memories"):
memories = obj.get_memories()
for memory in memories:
mapaddr = self.address_map(name, memory)
2013-07-28 10:33:36 -04:00
sram_bus = csr.Interface(*ifargs, **ifkwargs)
mmap = csr.SRAM(memory, mapaddr, bus=sram_bus)
2013-03-30 12:28:41 -04:00
self.submodules += mmap
csrs += mmap.get_csrs()
self.srams.append((name, memory, mapaddr, mmap))
if csrs:
2013-03-09 18:45:16 -05:00
mapaddr = self.address_map(name, None)
2013-07-28 10:33:36 -04:00
bank_bus = csr.Interface(*ifargs, **ifkwargs)
rmap = Bank(csrs, mapaddr, bus=bank_bus)
2013-03-30 12:28:41 -04:00
self.submodules += rmap
self.banks.append((name, csrs, mapaddr, rmap))
2013-03-09 18:45:16 -05:00
def get_rmaps(self):
2013-03-30 12:28:41 -04:00
return [rmap for name, csrs, mapaddr, rmap in self.banks]
2013-03-09 18:45:16 -05:00
def get_mmaps(self):
2013-03-30 12:28:41 -04:00
return [mmap for name, memory, mapaddr, mmap in self.srams]
2013-03-09 18:45:16 -05:00
def get_buses(self):
return [i.bus for i in self.get_rmaps() + self.get_mmaps()]