2013-06-11 08:18:16 -04:00
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from migen.fhdl.std import *
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2015-02-28 03:02:28 -05:00
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from misoclib.mem.sdram.bus import dfi, lasmibus
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from misoclib.mem.sdram.lasmicon.refresher import *
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from misoclib.mem.sdram.lasmicon.bankmachine import *
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from misoclib.mem.sdram.lasmicon.multiplexer import *
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2013-06-11 08:18:16 -04:00
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class LASMIcon(Module):
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2015-03-02 05:21:13 -05:00
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def __init__(self, phy, geom_settings, timing_settings):
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if phy.settings.memtype in ["SDR"]:
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burst_length = phy.settings.nphases*1 # command multiplication*SDR
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elif phy.settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
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burst_length = phy.settings.nphases*2 # command multiplication*DDR
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2013-06-11 08:18:16 -04:00
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address_align = log2_int(burst_length)
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self.dfi = dfi.Interface(geom_settings.mux_a,
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geom_settings.bank_a,
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2015-03-02 05:21:13 -05:00
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phy.settings.dfi_d,
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phy.settings.nphases)
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2013-06-11 08:18:16 -04:00
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self.lasmic = lasmibus.Interface(
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aw=geom_settings.row_a + geom_settings.col_a - address_align,
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2015-03-02 05:21:13 -05:00
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dw=phy.settings.dfi_d*phy.settings.nphases,
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2013-06-11 08:18:16 -04:00
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nbanks=2**geom_settings.bank_a,
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2013-06-17 17:33:57 -04:00
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req_queue_size=timing_settings.req_queue_size,
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2015-03-02 05:21:13 -05:00
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read_latency=phy.settings.read_latency+1,
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write_latency=phy.settings.write_latency+1)
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2013-06-11 08:18:16 -04:00
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self.nrowbits = geom_settings.col_a - address_align
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2014-10-17 05:14:35 -04:00
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2013-06-11 08:18:16 -04:00
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###
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self.submodules.refresher = Refresher(geom_settings.mux_a, geom_settings.bank_a,
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timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
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self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, address_align, i,
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getattr(self.lasmic, "bank"+str(i)))
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for i in range(2**geom_settings.bank_a)]
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2015-03-02 05:21:13 -05:00
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self.submodules.multiplexer = Multiplexer(phy, geom_settings, timing_settings,
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2013-06-11 08:18:16 -04:00
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self.bank_machines, self.refresher,
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self.dfi, self.lasmic)
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2013-06-15 06:51:11 -04:00
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def get_csrs(self):
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return self.multiplexer.get_csrs()
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