2014-09-24 08:28:52 -04:00
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from math import ceil
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2014-09-23 18:01:01 -04:00
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from migen.fhdl.std import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.fsm import FSM, NextState
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2014-09-24 08:28:52 -04:00
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from lib.sata.k7sataphy.std import *
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2014-09-27 11:26:52 -04:00
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def us(t, clk_freq):
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clk_period_us = 1000000/clk_freq
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2014-09-23 18:01:01 -04:00
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return ceil(t/clk_period_us)
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class K7SATAPHYHostCtrl(Module):
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2014-09-29 07:02:11 -04:00
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def __init__(self, gtx, crg, clk_freq):
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2014-09-27 10:10:39 -04:00
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self.ready = Signal()
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2014-09-23 18:01:01 -04:00
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2014-09-24 07:56:32 -04:00
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self.txdata = Signal(32)
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self.txcharisk = Signal(4)
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self.rxdata = Signal(32)
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2014-09-23 18:01:01 -04:00
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align_detect = Signal()
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2014-09-29 12:25:24 -04:00
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align_timeout_cnt = Signal(32)
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align_timeout = Signal()
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retry_timeout_cnt = Signal(32)
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retry_timeout = Signal()
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2014-09-24 08:28:52 -04:00
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non_align_cnt = Signal(4)
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2014-09-23 18:01:01 -04:00
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2014-09-24 05:07:36 -04:00
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txcominit = Signal()
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2014-09-24 08:28:52 -04:00
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txcomwake = Signal()
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2014-09-24 05:07:36 -04:00
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2014-09-24 08:28:52 -04:00
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fsm = FSM(reset_state="RESET")
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2014-09-23 18:01:01 -04:00
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self.submodules += fsm
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fsm.act("RESET",
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2014-09-27 10:10:39 -04:00
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gtx.txelecidle.eq(1),
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2014-09-29 07:02:11 -04:00
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If(crg.ready,
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2014-09-27 10:10:39 -04:00
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NextState("COMINIT")
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)
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)
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fsm.act("COMINIT",
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2014-09-23 18:01:01 -04:00
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gtx.txelecidle.eq(1),
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2014-09-27 11:26:52 -04:00
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txcominit.eq(1),
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2014-09-24 08:28:52 -04:00
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If(gtx.txcomfinish & ~gtx.rxcominitdet,
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2014-09-23 18:01:01 -04:00
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NextState("AWAIT_COMINIT")
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)
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)
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fsm.act("AWAIT_COMINIT",
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gtx.txelecidle.eq(1),
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If(gtx.rxcominitdet,
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NextState("AWAIT_NO_COMINIT")
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).Else(
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2014-09-29 12:25:24 -04:00
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If(retry_timeout,
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2014-09-23 18:01:01 -04:00
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NextState("RESET")
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)
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)
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)
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fsm.act("AWAIT_NO_COMINIT",
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gtx.txelecidle.eq(1),
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If(~gtx.rxcominitdet,
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NextState("CALIBRATE")
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)
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)
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fsm.act("CALIBRATE",
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gtx.txelecidle.eq(1),
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NextState("COMWAKE")
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)
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fsm.act("COMWAKE",
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gtx.txelecidle.eq(1),
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2014-09-24 05:07:36 -04:00
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txcomwake.eq(1),
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If(gtx.txcomfinish,
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2014-09-23 18:01:01 -04:00
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NextState("AWAIT_COMWAKE")
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)
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)
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fsm.act("AWAIT_COMWAKE",
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gtx.txelecidle.eq(1),
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If(gtx.rxcomwakedet,
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NextState("AWAIT_NO_COMWAKE")
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).Else(
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2014-09-29 12:25:24 -04:00
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If(retry_timeout,
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2014-09-23 18:01:01 -04:00
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NextState("RESET")
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)
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)
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)
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fsm.act("AWAIT_NO_COMWAKE",
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gtx.txelecidle.eq(1),
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If(~gtx.rxcomwakedet,
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2014-09-29 11:12:02 -04:00
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NextState("RESET_CRG")
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2014-09-23 18:01:01 -04:00
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)
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)
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2014-09-29 11:12:02 -04:00
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fsm.act("RESET_CRG",
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gtx.txelecidle.eq(0),
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crg.reset.eq(1),
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NextState("AWAIT_ALIGN")
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)
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2014-09-23 18:01:01 -04:00
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fsm.act("AWAIT_ALIGN",
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gtx.txelecidle.eq(0),
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2014-09-29 12:25:24 -04:00
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self.txdata.eq(0x4A4A4A4A), #D10.2
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self.txcharisk.eq(0b0000),
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gtx.rxalign.eq(1),
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2014-09-23 18:01:01 -04:00
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If(align_detect & ~align_timeout,
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NextState("SEND_ALIGN")
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).Elif(~align_detect & align_timeout,
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NextState("RESET")
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)
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)
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fsm.act("SEND_ALIGN",
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gtx.txelecidle.eq(0),
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2014-09-24 07:56:32 -04:00
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self.txdata.eq(ALIGN_VAL),
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self.txcharisk.eq(0b0001),
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2014-09-29 12:25:24 -04:00
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If(non_align_cnt == 3,
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2014-09-23 18:01:01 -04:00
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NextState("READY")
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)
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)
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fsm.act("READY",
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gtx.txelecidle.eq(0),
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If(gtx.rxelecidle,
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NextState("RESET")
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),
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2014-09-27 10:10:39 -04:00
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self.ready.eq(1)
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2014-09-23 18:01:01 -04:00
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)
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2014-09-24 05:07:36 -04:00
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txcominit_d = Signal()
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2014-09-24 05:37:28 -04:00
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txcomwake_d = Signal()
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2014-09-27 09:34:28 -04:00
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self.sync += [
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2014-09-25 08:52:16 -04:00
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txcominit_d.eq(txcominit),
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txcomwake_d.eq(txcomwake),
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2014-09-24 05:07:36 -04:00
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gtx.txcominit.eq(txcominit & ~txcominit_d),
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2014-09-25 08:52:16 -04:00
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gtx.txcomwake.eq(txcomwake & ~txcomwake_d),
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2014-09-24 05:07:36 -04:00
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]
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2014-10-16 04:38:26 -04:00
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self.comb += align_detect.eq(self.rxdata == ALIGN_VAL);
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2014-09-27 09:34:28 -04:00
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self.sync += \
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2014-09-24 05:07:36 -04:00
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If(fsm.ongoing("RESET"),
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2014-09-27 11:26:52 -04:00
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align_timeout_cnt.eq(us(873, clk_freq))
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2014-09-24 05:07:36 -04:00
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).Elif(fsm.ongoing("AWAIT_ALIGN"),
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align_timeout_cnt.eq(align_timeout_cnt-1)
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)
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self.comb += align_timeout.eq(align_timeout_cnt == 0)
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2014-09-27 09:34:28 -04:00
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self.sync += \
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2014-09-24 05:07:36 -04:00
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If(fsm.ongoing("RESET") | fsm.ongoing("AWAIT_NO_COMINIT"),
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2014-09-29 12:25:24 -04:00
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retry_timeout_cnt.eq(us(10000, clk_freq))
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2014-09-24 08:28:52 -04:00
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).Elif(fsm.ongoing("AWAIT_COMINIT") | fsm.ongoing("AWAIT_COMWAKE"),
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2014-09-29 12:25:24 -04:00
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retry_timeout_cnt.eq(retry_timeout_cnt-1)
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2014-09-24 05:07:36 -04:00
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)
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2014-09-29 12:25:24 -04:00
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self.comb += retry_timeout.eq(retry_timeout_cnt == 0)
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2014-09-24 05:07:36 -04:00
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2014-09-27 09:34:28 -04:00
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self.sync += \
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2014-09-24 05:07:36 -04:00
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If(fsm.ongoing("SEND_ALIGN"),
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2014-09-29 07:02:11 -04:00
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If(self.rxdata[0:8] == 0xBC,
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2014-09-24 05:07:36 -04:00
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non_align_cnt.eq(non_align_cnt + 1)
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).Else(
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non_align_cnt.eq(0)
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)
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2014-09-24 05:37:28 -04:00
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)
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2014-09-24 05:07:36 -04:00
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2014-09-23 18:01:01 -04:00
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class K7SATAPHYDeviceCtrl(Module):
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2014-09-29 07:02:11 -04:00
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def __init__(self, gtx, crg, clk_freq):
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2014-09-27 10:10:39 -04:00
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self.ready = Signal()
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2014-09-24 05:37:28 -04:00
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2014-09-24 07:56:32 -04:00
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self.txdata = Signal(32)
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self.txcharisk = Signal(4)
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self.rxdata = Signal(32)
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2014-09-24 05:37:28 -04:00
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align_detect = Signal()
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2014-09-29 12:25:24 -04:00
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align_timeout = Signal()
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align_timeout_cnt = Signal(32)
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retry_timeout_cnt = Signal(32)
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retry_timeout = Signal()
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2014-09-24 05:37:28 -04:00
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txcominit = Signal()
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2014-09-24 08:28:52 -04:00
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txcomwake = Signal()
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2014-09-24 05:37:28 -04:00
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2014-09-24 08:28:52 -04:00
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fsm = FSM(reset_state="RESET")
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2014-09-24 05:37:28 -04:00
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self.submodules += fsm
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fsm.act("RESET",
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2014-09-27 10:10:39 -04:00
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gtx.txelecidle.eq(1),
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2014-09-29 07:02:11 -04:00
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If(crg.ready,
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2014-09-27 10:10:39 -04:00
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NextState("AWAIT_COMINIT")
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)
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)
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fsm.act("AWAIT_COMINIT",
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2014-09-24 05:37:28 -04:00
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gtx.txelecidle.eq(1),
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If(gtx.rxcominitdet,
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2014-09-24 08:28:52 -04:00
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NextState("COMINIT")
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2014-09-24 05:37:28 -04:00
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)
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2014-10-16 04:38:26 -04:00
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)
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2014-09-24 05:37:28 -04:00
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fsm.act("COMINIT",
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gtx.txelecidle.eq(1),
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2014-09-27 11:26:52 -04:00
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txcominit.eq(1),
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2014-09-24 05:37:28 -04:00
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If(gtx.txcomfinish,
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NextState("AWAIT_COMWAKE")
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)
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)
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fsm.act("AWAIT_COMWAKE",
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gtx.txelecidle.eq(1),
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2014-09-24 08:28:52 -04:00
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If(gtx.rxcomwakedet,
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2014-09-24 05:37:28 -04:00
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NextState("AWAIT_NO_COMWAKE")
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).Else(
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2014-09-29 12:25:24 -04:00
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If(retry_timeout,
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2014-09-24 05:37:28 -04:00
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NextState("RESET")
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)
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)
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)
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fsm.act("AWAIT_NO_COMWAKE",
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gtx.txelecidle.eq(1),
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2014-09-24 08:28:52 -04:00
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If(~gtx.rxcomwakedet,
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2014-09-24 05:37:28 -04:00
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NextState("CALIBRATE")
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)
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)
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fsm.act("CALIBRATE",
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gtx.txelecidle.eq(1),
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NextState("COMWAKE")
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)
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fsm.act("COMWAKE",
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gtx.txelecidle.eq(1),
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2014-10-16 04:38:26 -04:00
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txcomwake.eq(1),
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2014-09-24 05:37:28 -04:00
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If(gtx.txcomfinish,
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2014-09-29 11:12:02 -04:00
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NextState("RESET_CRG")
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2014-09-24 05:37:28 -04:00
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)
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)
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2014-09-29 11:12:02 -04:00
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fsm.act("RESET_CRG",
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gtx.txelecidle.eq(0),
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crg.reset.eq(1),
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NextState("SEND_ALIGN")
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)
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2014-09-24 05:37:28 -04:00
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fsm.act("SEND_ALIGN",
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gtx.txelecidle.eq(0),
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2014-09-29 07:02:11 -04:00
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gtx.rxalign.eq(1),
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2014-09-24 07:56:32 -04:00
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self.txdata.eq(ALIGN_VAL),
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self.txcharisk.eq(0b0001),
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2014-09-24 05:37:28 -04:00
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If(align_detect,
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NextState("READY")
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2014-09-24 08:28:52 -04:00
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).Elif(align_timeout,
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2014-09-24 05:37:28 -04:00
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NextState("ERROR")
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)
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)
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fsm.act("READY",
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gtx.txelecidle.eq(0),
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NextState("READY"),
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If(gtx.rxelecidle,
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NextState("RESET")
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),
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2014-09-27 10:10:39 -04:00
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self.ready.eq(1)
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2014-09-24 05:37:28 -04:00
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)
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fsm.act("ERROR",
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gtx.txelecidle.eq(1),
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NextState("RESET")
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)
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txcominit_d = Signal()
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txcomwake_d = Signal()
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2014-09-27 09:34:28 -04:00
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self.sync += [
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2014-09-25 08:52:16 -04:00
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txcominit_d.eq(txcominit),
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txcomwake_d.eq(txcomwake),
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2014-09-24 05:37:28 -04:00
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gtx.txcominit.eq(txcominit & ~txcominit_d),
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gtx.txcomwake.eq(txcomwake & ~txcomwake),
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]
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2014-09-29 12:25:24 -04:00
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self.comb += align_detect.eq(self.rxdata == ALIGN_VAL);
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2014-09-27 09:34:28 -04:00
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self.sync += \
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2014-09-24 05:37:28 -04:00
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If(fsm.ongoing("RESET"),
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2014-09-27 11:26:52 -04:00
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align_timeout_cnt.eq(us(55, clk_freq))
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2014-09-24 05:37:28 -04:00
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).Elif(fsm.ongoing("AWAIT_ALIGN"),
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align_timeout_cnt.eq(align_timeout_cnt-1)
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)
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2014-09-24 08:28:52 -04:00
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self.comb += align_timeout.eq(align_timeout_cnt == 0)
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2014-09-27 11:26:52 -04:00
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self.sync += \
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If(fsm.ongoing("RESET"),
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2014-09-29 12:25:24 -04:00
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retry_timeout_cnt.eq(us(10000, clk_freq))
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2014-09-27 11:26:52 -04:00
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).Elif(fsm.ongoing("AWAIT_COMWAKE"),
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2014-09-29 12:25:24 -04:00
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retry_timeout_cnt.eq(retry_timeout_cnt-1)
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2014-09-27 11:26:52 -04:00
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)
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2014-09-29 12:25:24 -04:00
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self.comb += retry_timeout.eq(retry_timeout_cnt == 0)
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