2013-05-22 11:11:09 -04:00
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from migen.fhdl.std import *
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2014-01-26 16:19:43 -05:00
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from migen.sim.generic import run_simulation
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2012-03-05 14:31:41 -05:00
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2012-03-10 13:38:39 -05:00
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# Our simple counter, which increments at every cycle
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# and prints its current value in simulation.
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2013-07-24 12:47:25 -04:00
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class Counter(Module):
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2012-03-05 14:31:41 -05:00
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def __init__(self):
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2012-11-29 15:22:38 -05:00
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self.count = Signal(4)
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2013-07-24 12:47:25 -04:00
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# At each cycle, increase the value of the count signal.
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# We do it with convertible/synthesizable FHDL code.
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self.sync += self.count.eq(self.count + 1)
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2014-10-17 05:08:37 -04:00
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2012-03-10 13:38:39 -05:00
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# This function will be called at every cycle.
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2014-01-26 16:19:43 -05:00
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def do_simulation(self, selfp):
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2012-03-10 13:38:39 -05:00
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# Simply read the count signal and print it.
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# The output is:
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2014-10-17 05:08:37 -04:00
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# Count: 0
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2012-03-10 13:38:39 -05:00
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# Count: 1
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# Count: 2
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# ...
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2014-01-26 16:19:43 -05:00
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print("Count: " + str(selfp.count))
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2012-03-05 14:31:41 -05:00
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2014-01-26 16:19:43 -05:00
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if __name__ == "__main__":
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2012-03-06 09:00:02 -05:00
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dut = Counter()
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2014-01-26 16:19:43 -05:00
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# Since we do not use StopSimulation, limit the simulation
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2012-03-10 13:38:39 -05:00
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# to some number of cycles.
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2014-01-26 16:19:43 -05:00
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run_simulation(dut, ncycles=20)
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