litex/examples/pytholite/uio.py

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from migen.flow.network import *
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from migen.flow.transactions import *
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from migen.actorlib.sim import Dumper
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from migen.bus import wishbone
from migen.bus.transactions import *
from migen.uio.ioo import UnifiedIOSimulation
from migen.pytholite.transel import Register
from migen.pytholite.compiler import make_pytholite
from migen.sim.generic import Simulator
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from migen.fhdl.specials import Memory
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from migen.fhdl import verilog
layout = [("r", 32)]
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def gen():
ds = Register(32)
for i in range(3):
r = TRead(i, busname="mem")
yield r
ds.store = r.data
yield Token("result", {"r": ds})
for i in range(5):
r = TRead(i, busname="wb")
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yield r
ds.store = r.data
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yield Token("result", {"r": ds})
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class SlaveModel(wishbone.TargetModel):
def read(self, address):
return address + 4
def run_sim(ng):
g = DataFlowGraph()
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d = Dumper(layout)
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g.add_connection(ng, d)
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slave = wishbone.Target(SlaveModel())
intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], slave.bus)
c = CompositeActor(g)
fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
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sim = Simulator(fragment)
sim.run(50)
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del sim
def main():
mem = Memory(32, 3, init=[42, 37, 81])
dataflow = [("result", Source, layout)]
buses = {
"wb": wishbone.Interface(),
"mem": mem
}
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print("Simulating native Python:")
ng_native = UnifiedIOSimulation(gen(),
dataflow=dataflow,
buses=buses)
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run_sim(ng_native)
print("Simulating Pytholite:")
ng_pytholite = make_pytholite(gen,
dataflow=dataflow,
buses=buses)
run_sim(ng_pytholite)
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print("Converting Pytholite to Verilog:")
print(verilog.convert(ng_pytholite.get_fragment()))
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main()