104 lines
3.1 KiB
Python
104 lines
3.1 KiB
Python
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from migen.fhdl.std import *
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from migen.actorlib.fifo import AsyncFIFO
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from migen.actorlib.structuring import Converter
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from migen.flow.actor import Sink, Source
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from lib.sata.k7sataphy.std import *
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class K7SATAPHYRXAlign(Module):
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def __init__(self, dw=16):
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self.rxdata_i = Signal(dw)
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self.rxcharisk_i = Signal(dw//8)
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self.rxdata_o = Signal(dw)
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self.rxcharisk_o = Signal(dw//8)
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###
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rxdata_r = Signal(dw)
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rxcharisk_r = Signal(dw//8)
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self.sync.sata_rx += [
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rxdata_r.eq(self.rxdata_i),
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rxcharisk_r.eq(self.rxcharisk_i)
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]
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cases = {}
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cases[1<<0] = [
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self.rxdata_o.eq(rxdata_r[0:dw]),
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self.rxcharisk_o.eq(rxcharisk_r[0:dw//8])
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]
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for i in range(1, dw//8):
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cases[1<<i] = [
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self.rxdata_o.eq(Cat(self.rxdata_i[8*i:dw], rxdata_r[0:8*i])),
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self.rxcharisk_o.eq(Cat(self.rxcharisk_i[i:dw//8], rxcharisk_r[0:i]))
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]
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self.comb += Case(rxcharisk_r, cases)
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class K7SATAPHYRXConvert(Module):
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def __init__(self):
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self.rxdata = Signal(16)
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self.rxcharisk = Signal(2)
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self.source = Source([("data", 32), ("charisk", 4)])
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###
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# convert data widths
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rx_converter = RenameClockDomains(Converter([("raw", 16+2)], [("raw", 32+4)]), "sata_rx")
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self.submodules += rx_converter
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self.comb += [
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rx_converter.sink.stb.eq(1),
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rx_converter.sink.raw.eq(Cat(self.rxdata , self.rxcharisk)),
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rx_converter.source.ack.eq(1)
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]
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# clock domain crossing
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# SATA device is supposed to lock its tx frequency to its received rx frequency, so this
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# ensure that sata_rx and sata_tx clock have the same frequency with only not the same
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# phase and thus ensute the rx_fifo will never be full.
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rx_fifo = AsyncFIFO([("raw", 36)], 16)
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self.submodules.rx_fifo = RenameClockDomains(rx_fifo, {"write": "sata_rx", "read": "sys"})
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self.comb += [
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rx_converter.source.connect(self.rx_fifo.sink),
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self.rx_fifo.source.ack.eq(1),
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]
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# rearrange data
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self.comb += [
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self.source.stb.eq(self.rx_fifo.source.stb),
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self.source.payload.data.eq(Cat(rx_fifo.source.raw[0:16], rx_fifo.source.raw[18:18+16])),
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self.source.payload.charisk.eq(Cat(rx_fifo.source.raw[16:18], rx_fifo.source.raw[18+16:18+18])),
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self.rx_fifo.source.ack.eq(self.source.ack),
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]
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class K7SATAPHYTXConvert(Module):
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def __init__(self):
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self.sink = Sink([("data", 32), ("charisk", 4)])
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self.txdata = Signal(16)
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self.txcharisk = Signal(2)
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###
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# convert data widths
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tx_converter = RenameClockDomains(Converter([("raw", 32+4)], [("raw", 16+2)]), "sata_tx")
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self.submodules += tx_converter
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self.comb += [
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Cat(self.txdata, self.txcharisk).eq(tx_converter.source.raw),
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tx_converter.source.ack.eq(1),
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]
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# clock domain crossing
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tx_fifo = AsyncFIFO([("raw", 36)], 16)
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self.submodules.tx_fifo = RenameClockDomains(tx_fifo, {"write": "sys", "read": "sata_tx"})
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self.comb += [
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tx_fifo.source.connect(tx_converter.sink),
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self.tx_fifo.sink.stb.eq(1),
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]
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# rearrange data
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self.comb += [
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self.tx_fifo.sink.stb.eq(self.sink.stb),
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self.tx_fifo.sink.raw.eq(Cat(self.sink.data[0:16], self.sink.charisk[0:2],
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self.sink.data[16:32], self.sink.charisk[2:4])),
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self.sink.ack.eq(self.tx_fifo.sink.ack),
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]
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