litex/milkymist/dvisampler/__init__.py

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from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.bank.description import *
from milkymist.dvisampler.edid import EDID
from milkymist.dvisampler.clocking import Clocking
from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.charsync import CharSync
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from milkymist.dvisampler.decoding import Decoding
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from milkymist.dvisampler.chansync import ChanSync
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class DVISampler(Module, AutoReg):
def __init__(self, inversions=""):
self.submodules.edid = EDID()
self.sda = self.edid.sda
self.scl = self.edid.scl
self.submodules.clocking = Clocking()
self.clk = self.clocking.clkin
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for datan in "012":
name = "data" + str(datan)
invert = datan in inversions
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signame = name + "_n" if invert else name
s = Signal(name=signame)
setattr(self, signame, s)
cap = DataCapture(8, invert)
setattr(self.submodules, name + "_cap", cap)
self.comb += [
cap.pad.eq(s),
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cap.serdesstrobe.eq(self.clocking.serdesstrobe)
]
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charsync = CharSync()
setattr(self.submodules, name + "_charsync", charsync)
self.comb += charsync.raw_data.eq(cap.d)
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decoding = Decoding()
setattr(self.submodules, name + "_decod", decoding)
self.comb += [
decoding.valid_i.eq(charsync.synced),
decoding.input.eq(charsync.data)
]
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self.submodules.chansync = ChanSync()
self.comb += [
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self.chansync.valid_i.eq(self.data0_decod.valid_o & \
self.data1_decod.valid_o & self.data2_decod.valid_o),
self.chansync.data_in0.eq(self.data0_decod.output),
self.chansync.data_in1.eq(self.data1_decod.output),
self.chansync.data_in2.eq(self.data2_decod.output),
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]
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de = self.chansync.data_out0.de
r = self.chansync.data_out2.d
g = self.chansync.data_out1.d
b = self.chansync.data_out0.d
hsync = self.chansync.data_out0.c[0]
vsync = self.chansync.data_out0.c[1]