litex/examples/basic_sim.py

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# Copyright (C) 2012 Vermeer Manufacturing Co.
# License: GPLv3 with additional permissions (see README).
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from migen.fhdl.structure import *
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from migen.sim.generic import Simulator
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from migen.sim.icarus import Runner
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# Our simple counter, which increments at every cycle
# and prints its current value in simulation.
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class Counter:
def __init__(self):
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self.count = Signal(BV(4))
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# This function will be called at every cycle.
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def do_simulation(self, s):
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# Simply read the count signal and print it.
# The output is:
# Count: 0
# Count: 1
# Count: 2
# ...
print("Count: " + str(s.rd(self.count)))
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def get_fragment(self):
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# At each cycle, increase the value of the count signal.
# We do it with convertible/synthesizable FHDL code.
sync = [self.count.eq(self.count + 1)]
# List our simulation function in the fragment.
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sim = [self.do_simulation]
return Fragment(sync=sync, sim=sim)
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def main():
dut = Counter()
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# Use the Icarus Verilog runner.
# We do not specify a top-level object, and use the default.
sim = Simulator(dut.get_fragment(), Runner())
# Since we do not use sim.interrupt, limit the simulation
# to some number of cycles.
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sim.run(20)
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main()