2012-08-12 08:21:30 -04:00
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from fractions import Fraction
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from math import ceil
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import csr
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import migScope
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#
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2012-08-12 13:39:26 -04:00
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#Test Term
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2012-08-12 08:21:30 -04:00
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#
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#term = migScope.Term(32,True)
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#v = verilog.convert(term.get_fragment())
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#print(v)
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#
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#Test RangeDetector
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#
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#rangeDetector = migScope.RangeDetector (32,True)
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#v = verilog.convert(rangeDetector.get_fragment())
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#print(v)
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#
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#Test EdgeDetector
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#
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#edgeDetector = migScope.EdgeDetector (32,True,"RFB")
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#v = verilog.convert(edgeDetector.get_fragment())
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#print(v)
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#
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#Test Timer
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#
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#timer = migScope.Timer(32)
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#v = verilog.convert(timer.get_fragment())
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#print(v)
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#
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#Test Sum
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#
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2012-08-12 10:04:52 -04:00
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#sum = migScope.Sum(4,pipe=True)
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#v = verilog.convert(sum.get_fragment())
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#print(v)
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2012-08-12 08:21:30 -04:00
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#
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#Test MigIo
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#
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#migIo = migScope.MigIo(32,"IO")
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#v = verilog.convert(migIo.get_fragment())
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#print(v)
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#
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2012-08-12 11:31:15 -04:00
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#Test Storage
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2012-08-12 08:21:30 -04:00
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#
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2012-08-12 11:31:15 -04:00
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#storage = migScope.Storage(32,1024)
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#v = verilog.convert(storage.get_fragment())
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2012-08-12 10:04:52 -04:00
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#print(v)
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#
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#Test Sequencer
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#
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2012-08-12 11:31:15 -04:00
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#sequencer = migScope.Sequencer(1024)
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#v = verilog.convert(sequencer.get_fragment())
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#print(v)
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#
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#Test Recorder
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#
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2012-08-12 13:30:27 -04:00
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#recorder = migScope.Recorder(0,32,1024)
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#v = verilog.convert(recorder.get_fragment())
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#print(v)
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2012-08-12 13:39:26 -04:00
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#
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#Test Trigger
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#
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2012-08-12 13:30:27 -04:00
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term0 = migScope.Term(32)
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2012-08-12 13:39:26 -04:00
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term1 = migScope.RangeDetector(32)
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term2 = migScope.EdgeDetector(32)
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2012-08-12 13:30:27 -04:00
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term3 = migScope.Term(32)
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trigger0 = migScope.Trigger(0,32,64,[term0, term1, term2, term3])
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2012-08-12 15:17:17 -04:00
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#trigger0 = migScope.Trigger(0,32,64,[term0])
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2012-08-12 13:30:27 -04:00
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v = verilog.convert(trigger0.get_fragment())
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2012-08-12 11:31:15 -04:00
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print(v)
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2012-08-12 13:39:26 -04:00
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