87 lines
2.4 KiB
Coq
87 lines
2.4 KiB
Coq
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/*
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* Milkymist SoC
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* Copyright (c) 2010 Michael Walle
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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module jtag_cores (
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input [7:0] reg_d,
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input [2:0] reg_addr_d,
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output reg_update,
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output [7:0] reg_q,
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output [2:0] reg_addr_q,
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output jtck,
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output jrstn
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);
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wire tck;
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wire tdi;
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wire tdo;
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wire shift;
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wire update;
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wire reset;
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jtag_tap jtag_tap (
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.tck(tck),
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.tdi(tdi),
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.tdo(tdo),
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.shift(shift),
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.update(update),
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.reset(reset)
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);
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reg [10:0] jtag_shift;
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reg [10:0] jtag_latched;
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always @(posedge tck or posedge reset)
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begin
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if(reset)
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jtag_shift <= 11'b0;
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else begin
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if(shift)
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jtag_shift <= {tdi, jtag_shift[10:1]};
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else
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jtag_shift <= {reg_d, reg_addr_d};
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end
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end
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assign tdo = jtag_shift[0];
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always @(posedge reg_update or posedge reset)
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begin
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if(reset)
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jtag_latched <= 11'b0;
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else
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jtag_latched <= jtag_shift;
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end
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assign reg_update = update;
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assign reg_q = jtag_latched[10:3];
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assign reg_addr_q = jtag_latched[2:0];
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assign jtck = tck;
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assign jrstn = ~reset;
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endmodule
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