This website requires JavaScript.
Explore
Help
Sign In
Hardware
/
litex
mirror of
https://github.com/enjoy-digital/litex.git
Watch
1
Star
0
Fork
You've already forked litex
0
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Build your hardware, easily!
fpga
hardware
system-on-chip
13
Commits
37
Branches
13
Tags
46
MiB
C
53.2%
Python
43.1%
Assembly
1.4%
SystemVerilog
1.3%
Makefile
0.3%
Other
0.6%
f8d5c27ef8
Go to file
HTTPS
Download ZIP
Download TAR.GZ
Download BUNDLE
Clone in VS Code
Cite this repository
APA
BibTeX
Cancel
Sebastien Bourdeauducq
f8d5c27ef8
Wishbone: omit fixed LSBs
2012-01-13 17:28:58 +01:00
build
Initial import
2011-12-13 17:33:12 +01:00
milkymist
Wishbone: omit fixed LSBs
2012-01-13 17:28:58 +01:00
tb
/norflash
Convert -> convert
2012-01-05 19:27:45 +01:00
verilog
uart: new design using FHDL and bank (TX only, incomplete)
2011-12-18 00:29:37 +01:00
.gitignore
Initial import
2011-12-13 17:33:12 +01:00
build.py
Convert -> convert
2012-01-05 19:27:45 +01:00
constraints.py
Multiply system clock
2011-12-17 15:00:18 +01:00
top.py
convtools -> tools
2012-01-13 17:07:46 +01:00