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litex
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Build your hardware, easily!
13 Commits 37 Branches 13 Tags 46 MiB
C 53.2%
Python 43.1%
Assembly 1.4%
SystemVerilog 1.3%
Makefile 0.3%
Other 0.6%
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Sebastien Bourdeauducq f8d5c27ef8 Wishbone: omit fixed LSBs 2012-01-13 17:28:58 +01:00
build Initial import 2011-12-13 17:33:12 +01:00
milkymist Wishbone: omit fixed LSBs 2012-01-13 17:28:58 +01:00
tb/norflash Convert -> convert 2012-01-05 19:27:45 +01:00
verilog uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
.gitignore Initial import 2011-12-13 17:33:12 +01:00
build.py Convert -> convert 2012-01-05 19:27:45 +01:00
constraints.py Multiply system clock 2011-12-17 15:00:18 +01:00
top.py convtools -> tools 2012-01-13 17:07:46 +01:00