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master 0d58da0b57 · tools/litex_sim: Cleanup ethernet local/ip address handling and do +1 when both ethernet/etherbone are enabled. · Updated 2025-01-03 15:57:29 -05:00

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Branches

Dolu1990-patch-3 d55d07ecdb · Fix litex_setup.py OHCI clone · Updated 2024-12-11 06:05:56 -05:00	27 0	Included	ZIP  TAR.GZ
Dolu1990-patch-2 070c4cd387 · cores/cpu/vexiiriscv: Add PMP support · Updated 2024-11-26 11:40:03 -05:00	45 0	Included	ZIP  TAR.GZ
wuff 375940ad7d · soc/core/vexiiriscv: add macsg support (dma based ethernet) · Updated 2024-10-24 10:00:51 -04:00	100 0	Included	ZIP  TAR.GZ
urv 5f463dba87 · CHANGES.md: Update. · Updated 2024-10-17 11:45:50 -04:00	96 0	Included	ZIP  TAR.GZ
efinix_iface_signal_names 39d292a3c7 · build/efinix/common: Deprecate passing clk as str to avoid previous approach with pre-generated names. · Updated 2024-09-26 04:38:05 -04:00	142 0	Included	ZIP  TAR.GZ
usb_ohci_phy_fix 1f2418de3b · core/usb_ohci: fix SDRTristate clock · Updated 2024-09-05 04:17:22 -04:00	260 0	Included	ZIP  TAR.GZ
hyperram_new c554752e8a · soc/cores/hyperbus: Add automatic read burst detection. · Updated 2024-08-30 05:53:14 -04:00	218 0	Included	ZIP  TAR.GZ
hyperram_decoupling c857f7845e · soc/cores/hyperbus/HyperRAMPHY: Add specific sampling clk_domain. · Updated 2024-08-22 13:53:45 -04:00	224 10		ZIP  TAR.GZ
hyperbus_2x a88cee70c8 · test/test_hyperbus: Update. · Updated 2024-08-21 13:22:56 -04:00	225 0	Included	ZIP  TAR.GZ
hyperbus_io_regs 3a37d3ba98 · software/libbase/hyperram: Add missing #ifdef. · Updated 2024-08-20 11:11:02 -04:00	239 0	Included	ZIP  TAR.GZ
wishbone_dma_ctrl 4b745f9eba · soc/cores/dma: Add default parameters to add_ctrl. · Updated 2024-06-26 11:57:47 -04:00	336 0	Included	ZIP  TAR.GZ
liteeth_wishbone_tx_rx_buses 14a640302c · integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac. · Updated 2024-06-25 11:39:26 -04:00	340 0	Included	ZIP  TAR.GZ
ctu-can-fd 462016a1d0 · litex/tools/litex_json2dts_linux: Add initial CAN support. · Updated 2024-06-24 07:01:18 -04:00	339 0	Included	ZIP  TAR.GZ
ghdl_fix 5257ddaac0 · ci: Build/Install GHDL from sources. · Updated 2024-05-28 08:33:05 -04:00	465 0	Included	ZIP  TAR.GZ
zynqmp_aximaster_eth_i2c_uart 943c0c263d · soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP UART interface in EMIO mode · Updated 2024-05-17 05:02:41 -04:00	483 0	Included	ZIP  TAR.GZ
vexriscv_smp_irqs d4c1a10817 · cores/cpu/naxriscv: Add baremetal IRQ support · Updated 2024-05-14 08:57:29 -04:00	504 0	Included	ZIP  TAR.GZ
export_csr_c_rework 46911d5078 · soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects). · Updated 2024-05-14 05:59:13 -04:00	505 0	Included	ZIP  TAR.GZ
Dolu1990-patch-1 ea33e37b1a · cpu/naxriscv update mBus to preserve memory accesses offset · Updated 2024-04-25 10:06:34 -04:00	525 0	Included	ZIP  TAR.GZ
hyperbus_variable_latency ebabe82c70 · software/bios/main: Rewrite HyperRAM init/config. · Updated 2024-04-15 10:03:55 -04:00	562 0	Included	ZIP  TAR.GZ
gowin_emcu_uart 6c6c238309 · cpu/gowin_emcu: Switch to LiteX's UART (Using integrated UART is not really useful for now and make things less flexible, ie no UARTBone/Crossover possibilities). · Updated 2024-01-04 05:29:12 -05:00	729 1		ZIP  TAR.GZ