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3041150773 · Merge pull request #2021 from trabucayre/altera_agilex5_ddr_special · Updated 2024-07-26 12:26:19 -04:00
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Branches

wishbone_dma_ctrl

4b745f9eba · soc/cores/dma: Add default parameters to add_ctrl. · Updated 2024-06-26 11:57:47 -04:00
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liteeth_wishbone_tx_rx_buses

14a640302c · integration/soc/add_ethernet: Use separates TX/RX buses/regions for ethmac. · Updated 2024-06-25 11:39:26 -04:00
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ctu-can-fd

462016a1d0 · litex/tools/litex_json2dts_linux: Add initial CAN support. · Updated 2024-06-24 07:01:18 -04:00
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ghdl_fix

5257ddaac0 · ci: Build/Install GHDL from sources. · Updated 2024-05-28 08:33:05 -04:00
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zynqmp_aximaster_eth_i2c_uart

943c0c263d · soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP UART interface in EMIO mode · Updated 2024-05-17 05:02:41 -04:00
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vexriscv_smp_irqs

d4c1a10817 · cores/cpu/naxriscv: Add baremetal IRQ support · Updated 2024-05-14 08:57:29 -04:00
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export_csr_c_rework

46911d5078 · soc/integration/builder: Disable fields_access_functions generation by default since not widely used (at least not in LiteX "official" projects). · Updated 2024-05-14 05:59:13 -04:00
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Dolu1990-patch-1

ea33e37b1a · cpu/naxriscv update mBus to preserve memory accesses offset · Updated 2024-04-25 10:06:34 -04:00
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hyperbus_variable_latency

ebabe82c70 · software/bios/main: Rewrite HyperRAM init/config. · Updated 2024-04-15 10:03:55 -04:00
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gowin_emcu_uart

6c6c238309 · cpu/gowin_emcu: Switch to LiteX's UART (Using integrated UART is not really useful for now and make things less flexible, ie no UARTBone/Crossover possibilities). · Updated 2024-01-04 05:29:12 -05:00
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kianv

6598fe9c12 · cores/cpu: Add KianV CPU (RV32IMA) initial support. · Updated 2023-11-08 05:37:22 -05:00
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verilog_improvements_2

657252c573 · gen/fhdl/namer: Update copyrights. · Updated 2023-11-06 11:55:54 -05:00
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video_framebuffer_skip_first_frame

b0c0669ed3 · cores/video/VideoFramebuffer: Skip first frame on enable to ensure proper VTG/DMA synchronization. · Updated 2023-11-05 02:18:43 -05:00
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verilog_improvements

6f431fa2b1 · gen/fhdl: Cleanup/Simplify hierarchy generation. · Updated 2023-11-03 09:57:48 -04:00
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wishbone_word_byte_addressing

6e928efe82 · cores/cpu: Switch Wishbone interfaces to byte addressing where possible and remove address shifting. · Updated 2023-10-26 11:50:39 -04:00
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framebuffer_change

7617116c3e · build/generic_platform: Fix jtag_support typo. · Updated 2023-10-23 11:24:06 -04:00
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ci-dev-test

e0be028753 · litex_setup: Don't do repo init in dev_mode (SSH clone) if running on CI. · Updated 2023-09-18 03:20:48 -04:00
702
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efinix_fixes2

198acc630e · gen/fhdl/verilog: uses blocking affectation for comb always · Updated 2023-09-06 12:19:42 -04:00
717
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dma_nax

9b64f85e70 · wip DMA/NaxRiscv. · Updated 2023-09-01 05:26:41 -04:00
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allows_clk_name_override

6b018c4915 · soc/cores/clock/efinix: don't hardcore create_clock (fix warning because clock is created after set_false_path), explicit clock name (fix warning when signal is absorbed) · Updated 2023-08-31 10:07:12 -04:00
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