36 lines
1019 B
Python
36 lines
1019 B
Python
from migen.fhdl.structure import *
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from migen.fhdl import tools, verilog, autofragment
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from migen.bus import wishbone, csr, wishbone2csr
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from milkymist import m1reset, clkfx, lm32, norflash, uart
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import constraints
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def get():
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MHz = 1000000
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clk_freq = 80*MHz
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clkfx_sys = clkfx.Inst(50*MHz, clk_freq)
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reset0 = m1reset.Inst()
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cpu0 = lm32.Inst()
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norflash0 = norflash.Inst(25, 12)
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wishbone2csr0 = wishbone2csr.Inst()
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wishbonecon0 = wishbone.InterconnectShared(
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[cpu0.ibus, cpu0.dbus],
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[(0, norflash0.bus), (3, wishbone2csr0.wishbone)],
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register=True,
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offset=1)
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uart0 = uart.Inst(0, clk_freq, baud=115200)
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
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frag = autofragment.from_local()
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vns = tools.Namespace()
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src_verilog = verilog.convert(frag,
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{clkfx_sys.clkin, reset0.trigger_reset},
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name="soc",
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clk_signal=clkfx_sys.clkout,
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rst_signal=reset0.sys_rst,
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ns=vns)
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src_ucf = constraints.get(vns, clkfx_sys, reset0, norflash0, uart0)
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return (src_verilog, src_ucf)
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