2015-01-27 15:08:24 -05:00
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.. _about:
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================
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About LiteScope
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================
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2015-02-18 17:35:50 -05:00
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LiteScope is a small footprint and configurable embedded logic analyzer that you
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can use in your FPGA and aims to provide a free, portable and flexible
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2015-02-28 12:13:57 -05:00
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alternative to vendor's solutions!
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2015-01-27 15:08:24 -05:00
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2015-02-28 12:13:57 -05:00
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LiteScope is part of MiSoC libraries whose aims are to lower entry level of complex
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2015-02-21 17:34:08 -05:00
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FPGA cores by providing simple, elegant and efficient implementations of
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2015-01-27 15:08:24 -05:00
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components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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LiteScope uses technologies developed in partnership with M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LiteScope can be used as a Migen/MiSoC library (by simply installing it
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with the provided setup.py) or can be integrated with your standard design flow
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by generating the verilog rtl that you will use as a standard core.
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2015-02-28 12:13:57 -05:00
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LiteScope handles various export formats: .vcd, .sr(sigrok), .csv, .py...
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2015-01-27 15:08:24 -05:00
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Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
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external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
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.. _about-toolchain:
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Features
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========
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- IO peek and poke with LiteScopeIO
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- Logic analyser with LiteScopeLA:
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- Various triggering modules: Term, Range, Edge (add yours! :)
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- Run Length Encoder to "compress" data and increase recording depth
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- Subsampling
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- Storage qualifier
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- Data storage in block rams
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Possibles improvements
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======================
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- add standardized interfaces (AXI, Avalon-ST)
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- add protocols analyzers
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- add signals injection/generation
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- add storage in DRAM
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- add storage in HDD with LiteSATA core (to be released soon!)
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- add Ethernet Wishbone bridge
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- add PCIe Wishbone bridge with LitePCIe (to be released soon!)
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- ... See below Support and Consulting :)
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Support and Consulting
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======================
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We love open-source hardware and like sharing our designs with others.
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2015-02-28 12:13:57 -05:00
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LiteScope is mainly developed and maintained by EnjoyDigital.
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If you would like to know more about LiteScope or if you are already a happy user
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and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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Contact
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=======
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E-mail: florent [AT] enjoy-digital.fr
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