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xilinx_ise: fix clock domain names

This commit is contained in:
Sebastien Bourdeauducq 2013-03-23 19:37:16 +01:00
parent 797411c1a9
commit 003f1950cd
1 changed files with 3 additions and 3 deletions
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6
mibuild/xilinx_ise.py
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@ -17,7 +17,7 @@ TIMESPEC "TSclk" = PERIOD "GRPclk" """+str(period)+""" ns HIGH 50%;""", clk=clk)
class CRG_SE(SimpleCRG): class CRG_SE(SimpleCRG):
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert) SimpleCRG.__init__(self, platform, clk_name, rst_name, rst_invert)
_add_period_constraint(platform, self.cd.clk, period) _add_period_constraint(platform, self.cd_sys.clk, period)
class CRG_DS(Module): class CRG_DS(Module):
def __init__(self, platform, clk_name, rst_name, period, rst_invert=False): def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
@ -27,12 +27,12 @@ class CRG_DS(Module):
rst_n = platform.request(rst_name) rst_n = platform.request(rst_name)
self.comb += self.cd_sys.rst.eq(~rst_n) self.comb += self.cd_sys.rst.eq(~rst_n)
else: else:
platform.request(rst_name, None, self.cd.rst) platform.request(rst_name, None, self.cd_sys.rst)
_add_period_constraint(platform, self._clk.p, period) _add_period_constraint(platform, self._clk.p, period)
self.specials += Instance("IBUFGDS", self.specials += Instance("IBUFGDS",
Instance.Input("I", self._clk.p), Instance.Input("I", self._clk.p),
Instance.Input("IB", self._clk.n), Instance.Input("IB", self._clk.n),
Instance.Output("O", self.cd.clk) Instance.Output("O", self.cd_sys.clk)
) )
def _format_constraint(c): def _format_constraint(c):