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soc/itnegration: update litedram

This commit is contained in:
Florent Kermarrec 2019-09-09 15:12:08 +02:00
parent 19f58dd971
commit 004c96b508
2 changed files with 6 additions and 5 deletions
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4
litex/soc/integration/builder.py
View File

@ -16,7 +16,7 @@ import shutil
from litex.build.tools import write_to_file from litex.build.tools import write_to_file
from litex.soc.integration import cpu_interface, soc_core, soc_sdram from litex.soc.integration import cpu_interface, soc_core, soc_sdram
from litedram import sdram_init from litedram.init import get_sdram_phy_c_header
__all__ = ["soc_software_packages", "soc_directory", __all__ = ["soc_software_packages", "soc_directory",
"Builder", "builder_args", "builder_argdict"] "Builder", "builder_args", "builder_argdict"]
@ -125,7 +125,7 @@ class Builder:
if hasattr(self.soc, "sdram"): if hasattr(self.soc, "sdram"):
write_to_file( write_to_file(
os.path.join(generated_dir, "sdram_phy.h"), os.path.join(generated_dir, "sdram_phy.h"),
sdram_init.get_sdram_phy_c_header( get_sdram_phy_c_header(
self.soc.sdram.controller.settings.phy, self.soc.sdram.controller.settings.phy,
self.soc.sdram.controller.settings.timing)) self.soc.sdram.controller.settings.timing))

7
litex/soc/integration/soc_sdram.py
View File

@ -20,7 +20,7 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
class ControllerInjector(Module, AutoCSR): class ControllerInjector(Module, AutoCSR):
def __init__(self, phy, geom_settings, timing_settings, **kwargs): def __init__(self, phy, geom_settings, timing_settings, clk_freq, **kwargs):
self.submodules.dfii = dfii.DFIInjector( self.submodules.dfii = dfii.DFIInjector(
geom_settings.addressbits, geom_settings.addressbits,
geom_settings.bankbits, geom_settings.bankbits,
@ -30,7 +30,8 @@ class ControllerInjector(Module, AutoCSR):
self.comb += self.dfii.master.connect(phy.dfi) self.comb += self.dfii.master.connect(phy.dfi)
self.submodules.controller = controller = core.LiteDRAMController( self.submodules.controller = controller = core.LiteDRAMController(
phy.settings, geom_settings, timing_settings, **kwargs) phy.settings, geom_settings, timing_settings,
clk_freq, **kwargs)
self.comb += controller.dfi.connect(self.dfii.slave) self.comb += controller.dfi.connect(self.dfii.slave)
self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface) self.submodules.crossbar = core.LiteDRAMCrossbar(controller.interface)
@ -64,7 +65,7 @@ class SoCSDRAM(SoCCore):
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
self.submodules.sdram = ControllerInjector( self.submodules.sdram = ControllerInjector(
phy, geom_settings, timing_settings, **kwargs) phy, geom_settings, timing_settings, self.clk_freq, **kwargs)
main_ram_size = 2**(geom_settings.bankbits + main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits + geom_settings.rowbits +