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build: Rename VHDLWrapper to VHD2VConverter (more explicit).
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parent
848245bf59
commit
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2 changed files with 6 additions and 6 deletions
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@ -9,11 +9,11 @@ import os
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from migen import *
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# VHDLWrapper --------------------------------------------------------------------------------------
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# VHD2V Converter ----------------------------------------------------------------------------------
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class VHDLWrapper(Module):
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class VHD2VConverter(Module):
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"""
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VHDLWrapper simplify use of VHDL code: used to convert with ghdl the code if
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VHD2VConverter simplify use of VHDL code: used to convert with ghdl the code if
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needed or simply pass list of files to platform. May also add an Instance.
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Attributes
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==========
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@ -8,7 +8,7 @@ import os
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from migen import *
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from litex.build.VHDLWrapper import *
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from litex.build.vhd2v_converter import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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@ -99,7 +99,7 @@ class NEORV32(CPU):
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i_wb_err_i = idbus.err,
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)
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self.submodules.vhdlwrapper = VHDLWrapper(platform,
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self.submodules.vhd2v_converter = VHD2VConverter(platform,
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top_entity = "neorv32_litex_core_complex",
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build_dir = os.path.abspath(os.path.dirname(__file__)),
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work_package = "neorv32",
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@ -160,7 +160,7 @@ class NEORV32(CPU):
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# Download VHDL sources (if not already present).
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for directory, vhds in sources.items():
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for vhd in vhds:
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self.vhdlwrapper.add_source(os.path.join(cdir, vhd))
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self.vhd2v_converter.add_source(os.path.join(cdir, vhd))
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if not os.path.exists(os.path.join(cdir, vhd)):
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os.system(f"wget https://raw.githubusercontent.com/stnolting/neorv32/main/rtl/{directory}/{vhd} -P {cdir}")
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