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soc_sdram: remove upper limit on usable main RAM 

Revert commit #68a503174.
This commit is contained in:
Gabriel Somlo 2019-10-31 16:23:36 -04:00
parent ec831f5b63
commit 014db66444
1 changed files with 0 additions and 1 deletions
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litex/soc/integration/soc_sdram.py
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@ -61,7 +61,6 @@ class SoCSDRAM(SoCCore):
main_ram_size = 2**(geom_settings.bankbits + main_ram_size = 2**(geom_settings.bankbits +
geom_settings.rowbits + geom_settings.rowbits +
geom_settings.colbits)*phy.settings.databits//8 geom_settings.colbits)*phy.settings.databits//8
main_ram_size = min(main_ram_size, 0x20000000) # FIXME: limit to 512MB for now
# SoC [<--> L2 Cache] <--> LiteDRAM ---------------------------------------------------- # SoC [<--> L2 Cache] <--> LiteDRAM ----------------------------------------------------
if self.cpu.name == "rocket": if self.cpu.name == "rocket":