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MultiReg: remove idomain

This commit is contained in:
Sebastien Bourdeauducq 2013-03-15 19:51:29 +01:00
parent b2173bba9f
commit 0168f83523
2 changed files with 3 additions and 3 deletions
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4
milkymist/dvisampler/edid.py
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@ -33,9 +33,9 @@ class EDID(Module, AutoReg):
_sda_i_async = Signal() _sda_i_async = Signal()
self.sync += _sda_drv_reg.eq(sda_drv) self.sync += _sda_drv_reg.eq(sda_drv)
self.specials += [ self.specials += [
MultiReg(self.scl, "ext", scl_i, "sys"), MultiReg(self.scl, scl_i, "sys"),
Tristate(self.sda, 0, _sda_drv_reg, _sda_i_async), Tristate(self.sda, 0, _sda_drv_reg, _sda_i_async),
MultiReg(_sda_i_async, "ext", sda_i, "sys") MultiReg(_sda_i_async, sda_i, "sys")
] ]
# FIXME: understand what is really going on here and get rid of that workaround # FIXME: understand what is really going on here and get rid of that workaround

2
milkymist/uart/__init__.py
View File

@ -59,7 +59,7 @@ class UART(Module, AutoReg):
# RX # RX
rx = Signal() rx = Signal()
self.specials += MultiReg(self.rx, "ext", rx, "sys") self.specials += MultiReg(self.rx, rx, "sys")
rx_r = Signal() rx_r = Signal()
rx_reg = Signal(8) rx_reg = Signal(8)
rx_bitcount = Signal(4) rx_bitcount = Signal(4)