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cores/cpu: Switch to soc.bus.add_region instead or add_memory_region (now prefered).

This commit is contained in:
Florent Kermarrec 2023-02-20 11:19:12 +01:00
parent 01e9a54321
commit 019fac5653
3 changed files with 6 additions and 6 deletions
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2
litex/soc/cores/cpu/naxriscv/core.py
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@ -298,7 +298,7 @@ class NaxRiscv(CPU):
soc.irq.add("timer0", n=1) soc.irq.add("timer0", n=1)
# Add OpenSBI region. # Add OpenSBI region.
soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="cached+linker") soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
# Define ISA. # Define ISA.
soc.add_config("CPU_ISA", NaxRiscv.get_arch()) soc.add_config("CPU_ISA", NaxRiscv.get_arch())

8
litex/soc/cores/cpu/rocket/core.py
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@ -360,10 +360,10 @@ class Rocket(CPU):
# Get CPU Params. # Get CPU Params.
mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant] mem_dw, mmio_dw, num_cores = CPU_PARAMS[self.variant]
# Add OpenSBI/PLIC/CLINT regions. # FIXME: Just here for .dts generation through json2ds. # Add OpenSBI/PLIC/CLINT regions.
soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="linker") soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x00f0_0000, size= 0x8_0000, cached=False, linker=True)) # CHECKME.
soc.add_memory_region("plic", soc.mem_map.get("plic") , 0x400_0000, type="cached+linker") soc.bus.add_region("plic", soc_region_cls(origin=soc.mem_map.get("plic"), size=0x40_0000, cached=True, linker=True))
soc.add_memory_region("clint", soc.mem_map.get("clint") , 0x1_0000, type="cached+linker") soc.bus.add_region("clint", soc_region_cls(origin=soc.mem_map.get("clint"), size= 0x1_0000, cached=True, linker=True))
# Define number of CPUs # Define number of CPUs
soc.add_config("CPU_COUNT", num_cores) soc.add_config("CPU_COUNT", num_cores)

2
litex/soc/cores/cpu/vexriscv_smp/core.py
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@ -397,7 +397,7 @@ class VexRiscvSMP(CPU):
soc.irq.add("timer0", n=1) soc.irq.add("timer0", n=1)
# Add OpenSBI region. # Add OpenSBI region.
soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f0_0000, 0x8_0000, type="cached+linker") soc.bus.add_region("opensbi", soc_region_cls(origin=self.mem_map["main_ram"] + 0x00f0_0000, size=0x8_0000, cached=True, linker=True))
# Define number of CPUs # Define number of CPUs
soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count) soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)