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fixup: generated-verilog submodule for experimental Rocket support

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FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
This commit is contained in:
Gabriel L. Somlo 2019-05-23 16:27:17 -04:00
parent 1a530cf27d
commit 019fd94005
2 changed files with 4 additions and 0 deletions
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3
.gitmodules vendored
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@ -19,3 +19,6 @@
[submodule "litex/soc/cores/cpu/minerva/verilog"] [submodule "litex/soc/cores/cpu/minerva/verilog"]
path = litex/soc/cores/cpu/minerva/verilog path = litex/soc/cores/cpu/minerva/verilog
url = http://github.com/enjoy-digital/minerva-verilog url = http://github.com/enjoy-digital/minerva-verilog
[submodule "litex/soc/cores/cpu/rocket/verilog"]
path = litex/soc/cores/cpu/rocket/verilog
url = https://github.com/gsomlo/rocket-litex-verilog

1
litex/soc/cores/cpu/rocket/verilog Submodule

@ -0,0 +1 @@
Subproject commit bcb12b0233b050dddef8d9c69bbf590d10428647