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Merge pull request #1037 from thirtythreeforty/ecp5-pll 

Fix premature selection of full PLL config with no feedback
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enjoy-digital 2021-09-15 08:52:59 +02:00 committed by GitHub
parent 88d302d4db 91ec6e0da8
commit 02896a4a30
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2 changed files with 14 additions and 0 deletions
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5
litex/soc/cores/clock/lattice_ecp5.py
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@ -97,6 +97,9 @@ class ECP5PLL(Module):
break
if not valid:
all_valid = False
if self.nclkouts == self.nclkouts_max and not config["clkfb"]:
# If there is no output suitable for feedback and no spare, not valid
all_valid = False
else:
all_valid = False
if all_valid:
@ -159,4 +162,6 @@ class ECP5PLL(Module):
self.params[f"p_CLKO{n_to_l[n]}_FPHASE"] = 0
self.params[f"p_CLKO{n_to_l[n]}_CPHASE"] = cphase
self.params[f"o_CLKO{n_to_l[n]}"] = clk
if f > 0: # i.e. not a feedback-only clock
self.params["attr"].append((f"FREQUENCY_PIN_CLKO{n_to_l[n]}", str(f/1e6)))
self.specials += Instance("EHXPLLL", **self.params)

9
test/test_clock.py
View File

@ -121,6 +121,15 @@ class TestClock(unittest.TestCase):
pll.expose_dpa()
pll.compute_config()
# Test corner cases that have historically had trouble:
pll = ECP5PLL()
pll.register_clkin(Signal(), 100e6)
pll.create_clkout(ClockDomain("clkout1"), 350e6)
pll.create_clkout(ClockDomain("clkout2"), 350e6)
pll.create_clkout(ClockDomain("clkout3"), 175e6)
pll.create_clkout(ClockDomain("clkout4"), 175e6)
pll.compute_config()
# Lattice / NX
def test_nxpll(self):
pll = NXPLL()