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interconnect/ahb: Add AHB prefix to TransferType/Interface (similar to AXI).

This commit is contained in:
Florent Kermarrec 2024-01-04 15:21:32 +01:00
parent 55e2a1cec6
commit 02f0a96c84
2 changed files with 7 additions and 6 deletions
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7
litex/soc/cores/cpu/gowin_emcu/core.py
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@ -10,7 +10,8 @@ from migen import *
from litex.gen import * from litex.gen import *
from litex.soc.cores.cpu import CPU from litex.soc.cores.cpu import CPU
from litex.soc.interconnect import wishbone, ahb from litex.soc.interconnect import wishbone
from litex.soc.interconnect import ahb
# Gowin EMCU --------------------------------------------------------------------------------------- # Gowin EMCU ---------------------------------------------------------------------------------------
@ -160,7 +161,7 @@ class GowinEMCU(CPU):
i_NVSTR = 0 i_NVSTR = 0
) )
ahb_flash = ahb.Interface() ahb_flash = ahb.AHBInterface()
self.cpu_params.update( self.cpu_params.update(
o_TARGFLASH0HADDR = ahb_flash.addr, o_TARGFLASH0HADDR = ahb_flash.addr,
o_TARGFLASH0HBURST = ahb_flash.burst, o_TARGFLASH0HBURST = ahb_flash.burst,
@ -178,7 +179,7 @@ class GowinEMCU(CPU):
# Peripheral Bus (AHB -> Wishbone). # Peripheral Bus (AHB -> Wishbone).
# --------------------------------- # ---------------------------------
ahb_targexp0 = ahb.Interface() ahb_targexp0 = ahb.AHBInterface()
self.cpu_params.update( self.cpu_params.update(
o_TARGEXP0HADDR = ahb_targexp0.addr, o_TARGEXP0HADDR = ahb_targexp0.addr,
o_TARGEXP0HBURST = ahb_targexp0.burst, o_TARGEXP0HBURST = ahb_targexp0.burst,

6
litex/soc/interconnect/ahb.py
View File

@ -15,7 +15,7 @@ from litex.gen import *
# Helpers ------------------------------------------------------------------------------------------ # Helpers ------------------------------------------------------------------------------------------
class TransferType(IntEnum): class AHBTransferType(IntEnum):
"""Defines types of AHB transfers.""" """Defines types of AHB transfers."""
IDLE = 0 IDLE = 0
BUSY = 1 BUSY = 1
@ -24,7 +24,7 @@ class TransferType(IntEnum):
# AHB Interface ------------------------------------------------------------------------------------ # AHB Interface ------------------------------------------------------------------------------------
class Interface(Record): class AHBInterface(Record):
"""Sets up the AHB interface signals for master and slave.""" """Sets up the AHB interface signals for master and slave."""
adr_width = 32 adr_width = 32
data_width = 32 data_width = 32
@ -71,7 +71,7 @@ class AHB2Wishbone(LiteXModule):
ahb.readyout.eq(1), ahb.readyout.eq(1),
If(ahb.sel & If(ahb.sel &
(ahb.size <= log2_int(ahb.data_width//8)) & (ahb.size <= log2_int(ahb.data_width//8)) &
(ahb.trans == TransferType.NONSEQUENTIAL), (ahb.trans == AHBTransferType.NONSEQUENTIAL),
NextValue(wishbone.adr, ahb.addr[wishbone_adr_shift:]), NextValue(wishbone.adr, ahb.addr[wishbone_adr_shift:]),
NextValue(wishbone.dat_w, ahb.wdata), NextValue(wishbone.dat_w, ahb.wdata),
NextValue(wishbone.we, ahb.write), NextValue(wishbone.we, ahb.write),