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bank/csrgen: interface -> bus

This commit is contained in:
Sebastien Bourdeauducq 2012-12-06 17:15:47 +01:00
parent bec02c4783
commit 0392dd8ac2
1 changed files with 7 additions and 7 deletions
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14
top.py
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@ -114,13 +114,13 @@ def get():
fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb) fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub) asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
csrcon0 = csr.Interconnect(wishbone2csr0.csr, [ csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
uart0.bank.interface, uart0.bank.bus,
dfii0.bank.interface, dfii0.bank.bus,
identifier0.bank.interface, identifier0.bank.bus,
timer0.bank.interface, timer0.bank.bus,
minimac0.bank.interface, minimac0.bank.bus,
fb0.bank.interface, fb0.bank.bus,
asmiprobe0.bank.interface asmiprobe0.bank.bus
]) ])
# #