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lite*: finish ModuleTransformer adaptations (need to be tested on board)

This commit is contained in:
Florent Kermarrec 2015-04-08 23:27:22 +02:00
parent 3a2b677f85
commit 03aa972bb6
3 changed files with 10 additions and 10 deletions
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8
misoclib/com/liteeth/generic/__init__.py
View File

@ -29,15 +29,15 @@ class BufferizeEndpoints(ModuleTransformer):
# add buffer on sinks # add buffer on sinks
for name, sink in sinks.items(): for name, sink in sinks.items():
buf = Buffer(sink.description) buf = Buffer(sink.description)
self.submodules += buf submodule.submodules += buf
setattr(self, name, buf.d) setattr(self, name, buf.d)
self.comb += Record.connect(buf.q, sink) submodule.comb += Record.connect(buf.q, sink)
# add buffer on sources # add buffer on sources
for name, source in sources.items(): for name, source in sources.items():
buf = Buffer(source.description) buf = Buffer(source.description)
self.submodules += buf submodule.submodules += buf
self.comb += Record.connect(source, buf.d) submodule.comb += Record.connect(source, buf.d)
setattr(self, name, buf.q) setattr(self, name, buf.q)
class EndpointPacketStatus(Module): class EndpointPacketStatus(Module):

8
misoclib/mem/litesata/common.py
View File

@ -270,15 +270,15 @@ class BufferizeEndpoints(ModuleTransformer):
# add buffer on sinks # add buffer on sinks
for name, sink in sinks.items(): for name, sink in sinks.items():
buf = Buffer(sink.description) buf = Buffer(sink.description)
self.submodules += buf submodule.submodules += buf
setattr(self, name, buf.d) setattr(self, name, buf.d)
self.comb += Record.connect(buf.q, sink) submodule.comb += Record.connect(buf.q, sink)
# add buffer on sources # add buffer on sources
for name, source in sources.items(): for name, source in sources.items():
buf = Buffer(source.description) buf = Buffer(source.description)
self.submodules += buf submodule.submodules += buf
self.comb += Record.connect(source, buf.d) submodule.comb += Record.connect(source, buf.d)
setattr(self, name, buf.q) setattr(self, name, buf.q)
class EndpointPacketStatus(Module): class EndpointPacketStatus(Module):

4
misoclib/mem/litesata/core/link/__init__.py
View File

@ -35,7 +35,7 @@ class LiteSATALinkTX(Module):
# inserter CONT and scrambled data between # inserter CONT and scrambled data between
# CONT and next primitive # CONT and next primitive
cont = BufferizeEndpoints(LiteSATACONTInserter(phy_description(32)), "source") cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32)))
self.submodules += cont self.submodules += cont
# datas / primitives mux # datas / primitives mux
@ -121,7 +121,7 @@ class LiteSATALinkRX(Module):
self.submodules += fsm self.submodules += fsm
# CONT remover # CONT remover
cont = BufferizeEndpoints(LiteSATACONTRemover(phy_description(32)), "source") cont = BufferizeEndpoints("source")(LiteSATACONTRemover(phy_description(32)))
self.submodules += cont self.submodules += cont
self.comb += Record.connect(phy.source, cont.sink) self.comb += Record.connect(phy.source, cont.sink)