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soc/cores/clock/xilinx_us/USIDELAYCTRL: make sure sys clock domain is reseted when reference clock domain is reseted.

This commit is contained in:
Florent Kermarrec 2021-02-09 19:06:49 +01:00
parent 126dd267d6
commit 041aa9bf6f
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/clock/xilinx_us.py
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@ -93,7 +93,6 @@ class USMMCM(XilinxClocking):
class USIDELAYCTRL(Module): class USIDELAYCTRL(Module):
def __init__(self, cd_ref, cd_sys, reset_cycles=64, ready_cycles=64): def __init__(self, cd_ref, cd_sys, reset_cycles=64, ready_cycles=64):
cd_sys.rst.reset = 1
self.clock_domains.cd_ic = ClockDomain() self.clock_domains.cd_ic = ClockDomain()
ic_reset_counter = Signal(max=reset_cycles, reset=reset_cycles-1) ic_reset_counter = Signal(max=reset_cycles, reset=reset_cycles-1)
ic_reset = Signal(reset=1) ic_reset = Signal(reset=1)
@ -109,6 +108,7 @@ class USIDELAYCTRL(Module):
ic_ready = Signal() ic_ready = Signal()
self.comb += self.cd_ic.clk.eq(cd_sys.clk) self.comb += self.cd_ic.clk.eq(cd_sys.clk)
self.sync.ic += [ self.sync.ic += [
cd_sys.rst.eq(1),
If(ic_ready, If(ic_ready,
If(ic_ready_counter != 0, If(ic_ready_counter != 0,
ic_ready_counter.eq(ic_ready_counter - 1) ic_ready_counter.eq(ic_ready_counter - 1)